This thesis presents a design process for decreasing the power consumption of pulse-shaping filters (PSF), whose purpose is to limit radio transmissions to a specified channel. A hardware layout is assumed based on a low-power application, and a power model of the assumed hardware is developed that approximates the number of logic-stage output transitions that occur in the adder that computes the PSF output. The number of transitions is used as a cost function in a simulated annealing optimization routine that perturbs the ideal PSF coefficients in an effort to find a lower-cost alternative to the ideal PSF. The parameters that dictate the convergence properties of the simulated annealing routine were carefully tailored to this application. It is shown that, given enough time, the optimization routine will find a PSF that closely resembles the ideal PSF, but with considerably lower power consumption.
Using a set of PSFs that would be typical for this application, savings between 18.4% and 74.5% of dynamic power consumption were achieved with insignificant distortion of the frequency response. It is observed that the amount of distortion can be controlled by changing the distance that the coefficients may be perturbed from their ideal values. The data presented here suggest that this distance can be very small and significant power savings can still be found, and a limit is suggested as to how large this distance can be before the distortion in the frequency response of the optimized PSF begins to outweigh the savings in power.