The current thesis presents the design of a 10-bit Digital-to-Analog Converter (DAC) to be used in a Successive Approximation Register Analog-to-Digital converter (SAR ADC). The design implements a new architecture of current-mode MOSFET DAC referred to as a gate-controlled DAC, which is found to overcome the non-linearity problems faced by the conventional drain-controlled DAC. The design also achieves temperature-insensitive operation by operating the PMOS current sources at the Zero Temperature Coefficient (ZTC) voltage, when they are turned ON.
The transistor-level circuit of a 10-bit DAC in the proposed architecture is designed and laid out, and its functionality is verified by simulations. The resulting DAC transfer characteristic is monotonic and highly linear as a result of a gate-multiplication approach to the design of the current sources. The maximum absolute error associated with the proposed design is less than 1 LSB at 27C and slightly more than 1 LSB at 125C. An alternative design in which the current sources are designed using a width-customization approach is also simulated. This design has smaller die dimensions but is less accurate than the first design.