This thesis presents a real-time hardware implementation of a gradient domain high dynamic range compression algorithm; this technique is useful for processing high dynamic range (HDR) images to be able to view them on standard display devices. The hardware implementation is described in VHDL and synthesized for a field programmable gate array (FPGA) device. The maximum operating frequency achieved is fast enough to process high dynamic range videos with one megapixel per frame at a rate of about 100 frames per second. The hardware is tested on standard HDR images from the Debevec library. The output images have good visual quality and are similar to the output images obtained using floating-point arithmetic. An alternate hardware implementation that does not involve any multipliers is also discussed.
The inverse gradient transformation required for reconstructing back the image from the manipulated gradients is implemented by means of a local Poisson solver that utilizes only local information around each pixel along with special boundary conditions. The local Poisson solver requires a small and fixed amount of hardware and memory for any image size. The quality of the images obtained using our local Poisson solver for both fixed-point and floating-point implementations is compared to the quality of images produced by a system that solves the Poisson equation using a full-image fast Fourier transform (FFT).