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A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation

Abstract Details

2012, Master of Science, University of Akron, Electrical Engineering.
In this thesis, a 10-bit dual plate sampling capacitor DAC with reduced offset internal reference voltage generation is proposed. Instead of using the conventional two element switched capacitor circuit that consists of the charge sampling and summing capacitor, the proposed scheme performs the identical operation using a single capacitor without affecting the conversion speed. As a result, the capacitor area can be considerably reduced compared to conventional capacitive DACs, which eventually leads to power saving due to amplifier effective load reduction and feedback factor improvement. The auto-zero internal reference voltage generator replaces the resistive ladder voltage divider with two unit capacitors, reference amplifiers, and several switches which further reduces the area of the DAC. In addition, the effect of major non-idealities including reference voltage mismatch, capacitor mismatch, and parasitic capacitance are analyzed. The proposed DAC is implemented using CMOS 0.35µm technology with core size of 0.11mm2. The maximum INL and DNL measured in a fabricated circuit were 0.67 LSB and 0.33 LSB, respectively.
Kye-Shin Lee, Dr. (Advisor)
Joan Carletta, Dr. (Committee Member)
Robert Veillette, Dr. (Committee Member)
121 p.

Recommended Citations

Citations

  • Gaddam, R. S. (2012). A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation [Master's thesis, University of Akron]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=akron1349294825

    APA Style (7th edition)

  • Gaddam, Ravi Shankar. A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation. 2012. University of Akron, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=akron1349294825.

    MLA Style (8th edition)

  • Gaddam, Ravi Shankar. "A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation." Master's thesis, University of Akron, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=akron1349294825

    Chicago Manual of Style (17th edition)