Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


RavikumarN.the (final comments).pdf (1.4 MB)

ETD Abstract Container

Abstract Header

An Area Efficient 10-bit Time Mode Digital- to- Analog Converter with Current Settling Error Compensation Technique

Ravikumar, Nivethithaa
http://rave.ohiolink.edu/etdc/view?acc_num=akron1437756110

Abstract Details

2015, Master of Science in Engineering, University of Akron, Electrical Engineering.
This work describes an area efficient 10-bit time mode hybrid DAC with current settling error compensation. The proposed 10-bit hybrid DAC is realized using a current steering DAC for the lower bits conversion and a time mode DAC for the upper bits conversion. The time mode DAC consist of a single capacitor, amplifier, current mirror and several control switches which occupies less area than other DAC architectures. The time mode DAC current settling error occurs because of the capacitor current not immediately responding to the control pulse, which further decreases the DAC output voltage. A compensation pulse corresponding to the DAC error voltage is generated and is added to the control pulse to compensate the DAC output voltage error caused by improper current settling. In addition, the time mode DAC current settling error compensation does not critically increase the area. The proposed DAC is realized using 0.35µm CMOS technology with estimated core area of 0.00463mm2, which is less than most of the existing 10-bit DACs published in the literature. The maximum DNL and INL with error compensation showed 0.5LSB and -0.6LSB, respectively.
Kye Shin-Lee (Advisor)
45 p.
Electrical Engineering
area efficient; error compensation; hybrid DAC

Recommended Citations

Citations

  • Ravikumar, N. (2015). An Area Efficient 10-bit Time Mode Digital- to- Analog Converter with Current Settling Error Compensation Technique [Master's thesis, University of Akron]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=akron1437756110

    APA Style (7th edition)

  • Ravikumar, Nivethithaa. An Area Efficient 10-bit Time Mode Digital- to- Analog Converter with Current Settling Error Compensation Technique. 2015. University of Akron, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=akron1437756110.

    MLA Style (8th edition)

  • Ravikumar, Nivethithaa. "An Area Efficient 10-bit Time Mode Digital- to- Analog Converter with Current Settling Error Compensation Technique." Master's thesis, University of Akron, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=akron1437756110

    Chicago Manual of Style (17th edition)

akron1437756110
1,572
© 2015, all rights reserved.
This open access ETD is published by University of Akron and OhioLINK.