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zhang.pdf (2.79 MB)
ETD Abstract Container
Abstract Header
SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC
Author Info
ZHANG, GUANGLEI, ZHANG
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522
Abstract Details
Year and Degree
2018, Master of Science in Engineering, University of Akron, Electrical Engineering.
Abstract
This work presents a successive-approximation-register (SAR) analog-to-digital converter (ADC) using a single-capacitor-pulse-width-to-analog converter-based digital-to-analog (DAC). In the proposed SAR ADC, the single-capacitor DAC is realized by partially charging or discharging the sampling capacitor with a DC reference current. The charge and discharge time is determined by the pulse width of the control signal. As a result, a SAR ADC can be realized by using a single capacitor, a current source, a current mirror, a comparator, and control logic; the result is a significant reduction in the circuit area and a simplified switch control scheme, compared to conventional SAR ADCs using capacitor DACs. A 6-bit 500kS/s SAR ADC is designed using CMOS 0.35µm technology, and the operation is verified through circuit level simulations. The effect of non-idealities including capacitor error, comparator offset, and current mismatch are analyzed, where ADC INL and DNL with each error are obtained. The power consumption of the ADC core was 22.6µw, which is lower than other designs. Aside from the low power consumption, with the single capacitor switching technique, the chip size is significantly reduced. The chip size of the proposed SAR ADC is around 0.01mm2, which is 60% to 80% smaller than other recent SAR ADC architectures.
Committee
Kye-Shin Lee (Advisor)
Arjuna Madanayake (Committee Member)
Seungdeog Cho (Committee Member)
Pages
41 p.
Subject Headings
Electrical Engineering
Keywords
SAR ADC, Low power, small area
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Citations
ZHANG, ZHANG, G. (2018).
SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC
[Master's thesis, University of Akron]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522
APA Style (7th edition)
ZHANG, ZHANG, GUANGLEI.
SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC.
2018. University of Akron, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522.
MLA Style (8th edition)
ZHANG, ZHANG, GUANGLEI. "SAR ADC Using Single-Capacitor Pulse Width To Analog Converter Based DAC." Master's thesis, University of Akron, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1516622725471522
Chicago Manual of Style (17th edition)
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Document number:
akron1516622725471522
Download Count:
2,916
Copyright Info
© 2018, all rights reserved.
This open access ETD is published by University of Akron and OhioLINK.