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Testability insertion in bit-slice data path designs: A pseudo-exhaustive BIST approach

Soomro, Rahman Abdul
http://rave.ohiolink.edu/etdc/view?acc_num=case1057589169

Abstract Details

1994, Doctor of Philosophy, Case Western Reserve University, Computer Engineering.
Partition and test has been a time-saving method for exhaustive testing. I present a bit-sliced approach for exhaustive testing at system speed. The objective of this research is not to design a system, but to make the system testable. A method is introduced for producing exhaustive test patterns using LFSR-C (Linear Feedback Shift Register Counter) as a test pattern generator (TPG) for a two port ALU using a one phase clock. The scheme called Run-n-Hold scheme, generates test patterns at clock speed; in other words, the transitivity of test patterns is relatively high. Once the testing scheme is developed, test resource optimization is of much concern. Test resources consist of a test pattern generator and signature analyzer – LFSR-C and MISR (Multi-Input Signature Register). A bypass method is exploited for propagating test patterns to the ALU and response verification to the MISR. In this scheme, those ALUs and/or registers not in use during testing are used as bridges to pass the test patterns to the ALU under test and/or the test response to the designated MISR. If one ALU is used between test resource and the ALU under test, we call it one level, or one bypass. Serial testing is exploited in this research, which means one ALU is tested at a time. We have considered three ALU tes ting sequences: (1) random method: in this method the ALU sequence is arranged in a random order, then testing is conducted; (2) straight forward method: in this method the ALU sequence is arranged in a straight forward way; (3) hill climbing method: in this scheme the ALU test sequence is obtained by the well known hill climbing method. This method can be described briefly as follows: select an ALU to begin with, add another ALU to the sequence such that sequential combination of both ALUs gives a minimum area overhead; add another ALU until all ALUs are in the sequence. We selected the first ALU in random fashion and then added other ALUs according to the procedure described above. This selection did not give us the expected results. Alternatively, we started with the ALU whose input registers are connected to maximum number of ALUs in the data path. In the system testing mode the data buss is used for test pattern propagation, the system bus is used for response transmission to the designated MISR in the case of bypassing, and the system control bus is used for the test control. Finally, this test scheme is developed such that random testing can be accomplished with the same technique used for exhaustive testing; and exhaustive test controller can be used as the random test controller. (Abstract shortened by UMI.
Christos Papachristou (Advisor)
157 p.
Computer Science
Testability insertion bit-slice data path designs pseudo-exhaustive BIST approach

Recommended Citations

Citations

  • Soomro, R. A. (1994). Testability insertion in bit-slice data path designs: A pseudo-exhaustive BIST approach [Doctoral dissertation, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1057589169

    APA Style (7th edition)

  • Soomro, Rahman. Testability insertion in bit-slice data path designs: A pseudo-exhaustive BIST approach. 1994. Case Western Reserve University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1057589169.

    MLA Style (8th edition)

  • Soomro, Rahman. "Testability insertion in bit-slice data path designs: A pseudo-exhaustive BIST approach." Doctoral dissertation, Case Western Reserve University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=case1057589169

    Chicago Manual of Style (17th edition)

case1057589169
598
© 1994, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.