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ETD Abstract Container

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An FPGA Abstraction Layer for the Space Telecommunications Radio System

Nappier, Jennifer M.
http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556

Abstract Details

2009, Master of Sciences, Case Western Reserve University, EECS - System and Control Engineering.
The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the specialized signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. Extensions of the STRS Architecture Standard in the field programmable gate array (FPGA) were proposed. The extensions included a standard hardware abstraction layer for firmware in FPGAs. Current existing FPGA hardware abstraction layer standards were researched. These standards included the Joint Tactical Radio System (JTRS) Modem Hardware Abstraction Layer (MHAL), the WISHBONE Architecture, and the Open Core Protocol (OCP). The proposed STRS hardware abstraction layer was designed to provide standardized interfaces to the STRS waveform application running on the FPGA. Therefore, the waveform developer would not have to know a lot of information about the rest of the SDR platform. This standard hardware abstraction layer was called the Firmware Developer Interface (FDI). The FDI was implemented and tested on a laboratory breadboard SDR. The implementation and testing of the FDI on a laboratory breadboard SDR will be discussed.
Frank Merat, PhD (Advisor)
Marc Buchner, PhD (Committee Member)
Christos Papachristou, PhD (Committee Member)
39 p.
Electrical Engineering
waveforms; space communication; software reuse; firmware; FPGA; HAL

Recommended Citations

Citations

  • Nappier, J. M. (2009). An FPGA Abstraction Layer for the Space Telecommunications Radio System [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556

    APA Style (7th edition)

  • Nappier, Jennifer. An FPGA Abstraction Layer for the Space Telecommunications Radio System. 2009. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556.

    MLA Style (8th edition)

  • Nappier, Jennifer. "An FPGA Abstraction Layer for the Space Telecommunications Radio System." Master's thesis, Case Western Reserve University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=case1227033556

    Chicago Manual of Style (17th edition)

case1227033556
2,204
© 2008, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.