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Hardware Security through Design Obfuscation

Chakraborty, Rajat Subhra
http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481

Abstract Details

2010, Doctor of Philosophy, Case Western Reserve University, EECS - Computer Engineering.
Security of integrated circuits (ICs) has emerged as a major concern at different stages of IC life-cycle, spanning design, test, fabrication and deployment. Modern ICs are becoming increasingly vulnerable to various forms of security threats, such as: 1) illegal use of hardware intellectual property (IP) or “IP Piracy”; 2) illegal manufacturing of IC or “IC Piracy”; 3) insertion of malicious circuits, referred as “Hardware Trojan”, in a design to cause in-field circuit malfunction, and 4) leakage of secret information from an IC. These security threats are accentuated by current IC design practices, such as the widespread use of hardware IP modules to design complex system-on-chips (SoCs). In addition, the economics of electronic manufacturing dictates widespread outsourcing of integrated circuit fabrication to off-shore facilities, which increases the vulnerability to these attacks. In this research, we explore novel hardware design approaches that incorporate a key-based design obfuscation scheme to effectively protect a design against various security threats, while incurring low hardware and computational overheads. Obfuscation is a technique that makes comprehending and reverse-engineering a design difficult. To the best of our knowledge, this is the first effort to develop a systematic and provably robust hardware obfuscation approach that enables hardware protection at different stages of the IC life-cycle. Effectiveness of these approaches for protection against IP reverse-engineering and piracy, hardware Trojan and scan-based information leakage is evaluated with benchmark circuits and open-source IP cores. The obfuscation approaches are developed for both firm (gate-level) and soft (register transfer level) IPs. The principles of the obfuscation approach have been extended to protection of embedded software against piracy and malicious modification. An enhanced secure IC design flow with associated computer-aided design (CAD) tools is also developed.
Swarup Bhunia (Committee Chair)
Christos Papachristou (Committee Member)
Francis Merat (Committee Member)
David McIntyre (Committee Member)
Pankaj Rohatgi (Committee Member)
183 p.
Electrical Engineering
Hardware security; design obfuscation; hardware Trojan; statistical logic testing; secure scan design; software obfuscation; secure system-on-chip design

Recommended Citations

Citations

  • Chakraborty, R. S. (2010). Hardware Security through Design Obfuscation [Doctoral dissertation, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481

    APA Style (7th edition)

  • Chakraborty, Rajat. Hardware Security through Design Obfuscation. 2010. Case Western Reserve University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481.

    MLA Style (8th edition)

  • Chakraborty, Rajat. "Hardware Security through Design Obfuscation." Doctoral dissertation, Case Western Reserve University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1270133481

    Chicago Manual of Style (17th edition)

case1270133481
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© 2010, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.