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SiC JFET Device Modeling

Tian, David
http://rave.ohiolink.edu/etdc/view?acc_num=case1294852798

Abstract Details

2011, Master of Sciences, Case Western Reserve University, EECS - Electrical Engineering.
This work involves modeling the SiC JFET developed at Case Western Reserve University. First, a primer and background to the topic are given. Next, enhancements to DC modeling are described, including the implementation of a more accurate mobility model and a parameter set optimized for the Case Western SiC JFETs. The issue of convergence in SPICE simulation is addressed and a new square-law Verilog-A model is described. Finally, capacitance models for the SiC JFET are verified in SPICE.
Steven Garverick (Committee Chair)
Christian Zorman (Committee Member)
Swarup Bhunia (Committee Member)
97 p.
Electrical Engineering
silicon carbide; JFET; device modeling; high temperature

Recommended Citations

Citations

  • Tian, D. (2011). SiC JFET Device Modeling [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1294852798

    APA Style (7th edition)

  • Tian, David. SiC JFET Device Modeling. 2011. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1294852798.

    MLA Style (8th edition)

  • Tian, David. "SiC JFET Device Modeling." Master's thesis, Case Western Reserve University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1294852798

    Chicago Manual of Style (17th edition)

case1294852798
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© 2011, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.