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An Area-Efficient Architecture for the Implementation of LDPC Decoder

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2011, Master of Sciences (Engineering), Case Western Reserve University, EECS - Computer Engineering.
Due to its near Shannon limit performance in high speed communication, low-density parity check (LDPC) code has performed a strong comeback recent years. In this work, a partial parallel decoding architecture is proposed based on a column-layered LDPC decoding scheme [2]. The purpose of this work is to make a tradeoff between area cost and throughput. I construct the structure of the partial parallel decoder, and compare its throughput and area cost with the design in [2]. Then I obtain the synthesis results of my design with Xilinx FPGA tool. The device utilization summary and timing summary are provided at the end of this work. Comparing with the design in [2], the partial parallel design in my work needs much less hardware resources. As a result, when the area is limit and a lower throughput is acceptable, my design can be considered instead of the design in [2].
Xinmiao Zhang (Committee Chair)
Christos Papachristou (Committee Member)
Daniel Saab (Committee Member)
52 p.

Recommended Citations

Citations

  • Yang, L. (2011). An Area-Efficient Architecture for the Implementation of LDPC Decoder [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576

    APA Style (7th edition)

  • Yang, Lan. An Area-Efficient Architecture for the Implementation of LDPC Decoder. 2011. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576.

    MLA Style (8th edition)

  • Yang, Lan. "An Area-Efficient Architecture for the Implementation of LDPC Decoder." Master's thesis, Case Western Reserve University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576

    Chicago Manual of Style (17th edition)