Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


case1307667225.pdf (1.49 MB)

ETD Abstract Container

Abstract Header

Noise Margin, Critical Charge and Power-Delay Tradeoffs for SRAM Design Space Exploration

Rajendran, Aravind
http://rave.ohiolink.edu/etdc/view?acc_num=case1307667225

Abstract Details

2011, Master of Sciences (Engineering), Case Western Reserve University, EECS - Electrical Engineering.
Aggressive technology scaling in semiconductor devices has resulted in stability reduction for classic SRAM designs. This is especially problematic for large integrated circuits. The stability of SRAM cells can be affected by noise during a read operation and radiation during the standby mode. In this work, an approach to address the gradual stability reduction in SRAM designs is presented. An SRAM design trade-offs approach is presented which improves the characteristics of SRAM by modulating the transistor sizing ratio, β. This method was tested on various SRAM designs in 32 nm technology. SRAM designs were optimized for various constraints in power consumption, performance, radiation tolerance and data stability. Different design trends produced by the extensive approach analysis is discussed in this thesis.
Chriostos Papachristou, PhD (Committee Chair)
Frank Merat, PhD (Committee Member)
Daniel Saab, PhD (Committee Member)
63 p.
Electrical Engineering
SRAM; Stability; Static Noise Margin; Butterfly Curve; Soft Error; Critical Charge

Recommended Citations

Citations

  • Rajendran, A. (2011). Noise Margin, Critical Charge and Power-Delay Tradeoffs for SRAM Design Space Exploration [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1307667225

    APA Style (7th edition)

  • Rajendran, Aravind. Noise Margin, Critical Charge and Power-Delay Tradeoffs for SRAM Design Space Exploration. 2011. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1307667225.

    MLA Style (8th edition)

  • Rajendran, Aravind. "Noise Margin, Critical Charge and Power-Delay Tradeoffs for SRAM Design Space Exploration." Master's thesis, Case Western Reserve University, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1307667225

    Chicago Manual of Style (17th edition)

case1307667225
3,389
© 2011, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.