Reconfigurable computing platforms that offer the flexibility to configure hardware resources
according to application requirements, provide great opportunity to accelerate wide variety
of applications. Over the past decade, Field Programmable Gate Arrays (FPGAs) have grown to be the most popular hardware reconfigurable
computing platform. Modern FPGAs integrate an array of spatially distributed logic/memory
blocks and programmable routing resources. Such a framework can provide several orders of magnitude more throughput compared to conventional microprocessor
based designs. The power and performance of conventional FPGA platform is largely dominated by programmable
interconnects, which have poor technological scalability. Moreover, the performance improvement for applications
mapped to the FPGA platform is largely limited by the off-chip bandwidth. A reconfigurable framework which
minimizes the contribution from the programmable interconnects and mitigates the bandwidth bottleneck by
moving the computing engine close to the data is expected to significantly improve the energy efficiency of reconfigurable systems.
In this work, we propose a novel hardware reconfigurable framework, referred to as memory based
computing (MBC) framework. The main computing fabric for such a framework
is a 2-D memory array which is used to store the functional behavior for the mapped application.
Each computing element in the framework is temporal in nature and an array of these elements is
used to map an application in a spatio-temporal fashion. Temporal execution inside each
compute element reduces the requirement for programmable interconnects, thus improving
the energy-efficiency over a fully spatial reconfigurable framework. In addition to storing
the functional behavior, the memory arrays also store data, thus mitigating the off-chip bandwidth bottleneck.
The framework is particularly appealing for system design with many emerging non-silicon nano-devices, which are amenable to dense, regular nonvolatile memory design. With the primary computing fabric
being memory, the proposed MBC framework can be made robust
to high device failure rates at nanoscale technologies. We have developed architecture
and circuit level optimization techniques for the proposed framework along with efficient
algorithms for automatic mapping of applications to this framework. Finally, we have investigated
application of this framework as a reconfigurable computing resource in a processor for
reliability improvement and hardware acceleration.