With CMOS technology scaling into deep nanoscale level, reliability issues have emerged as key concerns for SRAM memories. The reliability of SRAM memories is critical for the overall reliability of the modern ICs because memories occupy a large portion of the chip area. SRAM memory susceptibility to soft errors caused by ionizing particles significantly increases due to small node capacitance.
Further aggressive technology scaling is reaching its saturation due to limitations posed by physics on transistor size reduction. Emerging 3D through-silicon vias (TSV) chip integration can provide an alternative solution to satisfy ever-growing demands for packing density. However, increased heat generation per unit footprint and poor heat dissipation in 3D stacks can lead to high chip temperatures, thus thermal management is considered one of the most critical reliability issues in 3D ICs.
This work addresses the most urgent reliability concerns in conventional SRAM memories caused by soft errors and in emerging 3D TSV ICs caused by excessive heat generation, respectively.
In this research, a new methodology based on functional component separation, for the design of soft error tolerant SRAM cells, is presented. The methodology is applied to develop several novel SRAM cell designs with improved soft error tolerance.
Novel hardened SRAM cell designs using on-demand protective capacitor circuitry and tri-state inverters are developed based on the proposed methodology of functional separation. The developed SRAM designs offer high soft error protection level. In addition to soft error robustness, the tri-state based SRAM cells demonstrate excellent write performance, low power consumption, and high read cell stability, and are scalable into the deep nanoscale region.
A new 3D analytical thermal model is developed to simulate temperature fields in 3D TSV ICs. The model allows for consideration of inhomogeneous localized heating sources, heat exchange within the layer, heat transfer through external surfaces of the device, inter-layer heat transfer with possible inhomogeneous TSV placement, and micro-channel cooling. The model is applied to analyze the steady state thermal behavior of 3D TSV devices with inhomogeneous power densities. The model has a high computational efficiency, and allows simulations to be performed in real time.