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Hardware Emulation of Sequential ATPG-Based Bounded Model Checking

Ford, Gregory Fick

Abstract Details

2014, Master of Sciences (Engineering), Case Western Reserve University, EECS - Computer Engineering.
The size and complexity of integrated circuits is continually increasing, in accordance with Moore’s law. Along with this growth comes an expanded exposure to subtle design errors, thus leaving a greater burden on the process of formal verification. Existing methods for formal verification, including Automatic Test Pattern Generation (ATPG) are susceptible to exploding model sizes and run times for larger and more complex circuits. In this paper, a method is presented for emulating the process of sequential ATPG-based Bounded Model Checking on reconfigurable hardware. This achieves a speed up over software based methods, due to the fine-grain massive parallelism inherent to hardware.
Daniel Saab (Committee Chair)
Francis Merat (Committee Member)
Christos Papachristou (Committee Member)
266 p.

Recommended Citations

Citations

  • Ford, G. F. (2014). Hardware Emulation of Sequential ATPG-Based Bounded Model Checking [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165

    APA Style (7th edition)

  • Ford, Gregory. Hardware Emulation of Sequential ATPG-Based Bounded Model Checking. 2014. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.

    MLA Style (8th edition)

  • Ford, Gregory. "Hardware Emulation of Sequential ATPG-Based Bounded Model Checking." Master's thesis, Case Western Reserve University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165

    Chicago Manual of Style (17th edition)