Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


AnuradhaJangid_Thesis_F.pdf (2.32 MB)

ETD Abstract Container

Abstract Header

Verifying IP-Cores by Mapping Gate to RTL-Level Designs

Jangid, Anuradha
http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878

Abstract Details

2013, Master of Sciences (Engineering), Case Western Reserve University, EECS - Computer Engineering.
Since 1965, with the invention of Integrated Circuit (IC) devices, the number of transistors on ICs has doubled every two years, as predicted by Moore. Today, the scaling of digital ICs has reached a point where it contains billions of interconnected transistors. As anticipated by International Technology Roadmap for Semiconductors (ITRS), mass production of silicon will contain over 6.08 billion transistors per chip by 2014, based on 14nm design technology standards. This humongous density of transistors places immense pressure on verification of IC designs at each stage of silicon development. Hardware Verification is the process of validating the correctness of a design implemented from the design specs. It accounts to nearly 70% - 80% of the total efforts in an IC development process. To validate the implementation, a typical silicon development cycle includes functional, logic and layout verifications processes. Therefore, it is desirable to incorporate a standard verification methodology which can certify point to point symmetry between the designs at different abstraction levels. Moreover, if such a methodology is applied, it would facilitate early detection of hardware defects which might arise from design synthesis, thereby, reducing the verification efforts in silicon development. In our work, we introduce a novel technique to verify the implementation of an IC at different design phases. Our technique is based on mapping of design models, by using Distinguishing Experiment, Distinguishing Sequence Generation, Simulation and Automatic Test Pattern Generation (ATPG). ATPG produces input sequences; such that when these sequences are applied on a pair of gates from a circuit, they generate different logic values at their corresponding outputs. Both designs are simulated with these input sequences and based on the simulation results, a distinguishing tree is constructed. Our technique utilizes a recursive simulation approach where feedback to distinguishing sequence generation module is provided by the tree after each simulation. Intelligence drawn from distinguishing tree states correspondence or mismatch between designs. A System on Chip (SoC) is an IC design, containing wide range of Intellectual Property (IP) cores. Verifying the equivalency of these IP cores at different abstraction levels, such as - Register Transfer Level (RTL) and gate-level, is extremely important. Our approach requires examination of gate-level design and its equivalent RTL-level design to identify the correspondence between gates and wires/variables. For the implementation, we are proposing an algorithm which accepts the gate and an RTL level circuits, matches the wires/variables in RTL-level design to the gates in gate level-design and identifies the location(s) where the two descriptions differ (if any) from each other. Similarly, a mapping of gates from Gate-level and transistors (pMOS, nMOS) from layout-level design can be established. Our methodology is applicable to both combinational and sequential designs. We designed an algorithm based on the Time Frame Expansion concept in sequential ATPG. This algorithm generates distinguishing input sequence for both classes of circuits. We have used several heuristics to improvise our ATPG algorithm in terms of speed, efficiency, for example; loop avoidance, controllability to select objective and guide backtrack, unreachable state, etc. For asserting our approach, we have performed various experiments on standard designs, which include ALU, USB 2.0 and Open RISC 1200, wherein we have successfully established a correspondence between the designs. Also, we have introduced several variances in both the designs and carried out experiments to identify those differences and to evaluate the precision and efficiency of our approach.
Daniel G Saab (Advisor)
Computer Engineering; Design; Systems Design
Distinguishing Sequence, Distinguishing Experiments, Distinguishing Tree Generation

Recommended Citations

Citations

  • Jangid, A. (2013). Verifying IP-Cores by Mapping Gate to RTL-Level Designs [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878

    APA Style (7th edition)

  • Jangid, Anuradha. Verifying IP-Cores by Mapping Gate to RTL-Level Designs. 2013. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878.

    MLA Style (8th edition)

  • Jangid, Anuradha. "Verifying IP-Cores by Mapping Gate to RTL-Level Designs." Master's thesis, Case Western Reserve University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1385975878

    Chicago Manual of Style (17th edition)

case1385975878
1,061
© 2013, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.