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Chris Babecki MS Thesis.pdf (1.4 MB)

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Abstract Header

A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications

Babecki, Christopher
http://orcid.org/0000-0002-5253-0113
http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331

Abstract Details

2015, Master of Sciences (Engineering), Case Western Reserve University, EECS - Electrical Engineering.
Security is becoming an increasing concern in today's computer applications. Unfortunately, most encryption/decryption algorithms are computationally expensive and often do not map efficiently to general purpose processors (GPPs) or reconfigurable fabrics like Field Programmable Gate Arrays (FPGAs). Fixed-function accelerators offer significant improvement in energy-efficiency, but they do not allow more than one application to reuse hardware resources. This work presents a new reconfigurable hardware framework called Memory-Array centric Hardware Accelerator (MAHA) for accelerating a wide array of security applications. It incorporates a coarse-grained datapath, support for lookup functions, and flexible interconnect optimizations, which enable on-demand pipelining and parallel computations in multiple light-weight processing elements. Through simulations, this work compares the performance of MAHA to a commercial GPPs and FPGAs. Results for a set of six common security applications show comparable latency between MAHA and FPGA implementations with 2.5X improvement in energy-delay product and 4X improvement in iso-area throughput.
Swarup Bhunia, Ph.D. (Advisor)
Soumyajit Mandal, Ph.D. (Committee Member)
Daniel Saab, Ph.D. (Committee Member)
119 p.
Computer Engineering
security applications; domain-specific hardware accelerator; energy-efficiency; reconfigurable computing; side-channel attack resistance

Recommended Citations

Citations

  • Babecki, C. (2015). A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331

    APA Style (7th edition)

  • Babecki, Christopher. A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications. 2015. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331.

    MLA Style (8th edition)

  • Babecki, Christopher. "A Memory-Array Centric Reconfigurable Hardware Accelerator for Security Applications." Master's thesis, Case Western Reserve University, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=case1427381331

    Chicago Manual of Style (17th edition)

case1427381331
421
© 2015, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.