Skip to Main Content
 

Global Search Box

 
 
 
 

Files

File List


Kevin_Perera_Thesis.pdf (2.64 MB)

ETD Abstract Container

Abstract Header

An Automatable Workflow to Analyze and Secure Integrated Circuits Against Power Analysis Attacks

Perera, Kevin
http://rave.ohiolink.edu/etdc/view?acc_num=case1491319301653169

Abstract Details

2017, Master of Sciences (Engineering), Case Western Reserve University, EECS - Computer Engineering.
This thesis presents a workflow that will analyze and secure a circuit during its synthesis stage, based on a security level specified by the designer. The workflow applies the security measures at the gate level. The workflow has three main stages; synthesis, analysis and substitution. After synthesizing and levelizing the circuit; observability and controllability, testability measures are used to determine the vulnerabilities of gates. Once vulnerable gates are determined they are replaced with gates that perform the same operation, but has measures to prevent power analysis attacks. Experimental results are provided of preliminary experiments carried out to determine the feasibility of gate level solutions to counteract power analysis attacks. The AES algorithm was chosen to apply the work flow in order to verify its effectiveness and the results from this experiment indicate that applying the workflow substantially increased the circuit’s resilience against power analysis attacks.
Daniel Saab, PhD (Advisor)
Christos Papachristou, PhD (Committee Member)
Ming-Chun Huang, PhD (Committee Member)
90 p.
Computer Engineering
Differential Power Analysis; Side Channel Attack; Advanced encryption standard; Countermeasure

Recommended Citations

Citations

  • Perera, K. (2017). An Automatable Workflow to Analyze and Secure Integrated Circuits Against Power Analysis Attacks [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1491319301653169

    APA Style (7th edition)

  • Perera, Kevin. An Automatable Workflow to Analyze and Secure Integrated Circuits Against Power Analysis Attacks . 2017. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1491319301653169.

    MLA Style (8th edition)

  • Perera, Kevin. "An Automatable Workflow to Analyze and Secure Integrated Circuits Against Power Analysis Attacks ." Master's thesis, Case Western Reserve University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=case1491319301653169

    Chicago Manual of Style (17th edition)

case1491319301653169
260
© 2017, all rights reserved.
This open access ETD is published by Case Western Reserve University School of Graduate Studies and OhioLINK.