Skip to Main Content
 

Global Search Box

 
 
 
 

ETD Abstract Container

Abstract Header

XBT: FPGA Accelerated Binary Translation

Abstract Details

2021, Master of Sciences, Case Western Reserve University, EECS - Computer Engineering.
Binary translation (BT) is the process of converting executable binary from one instruction set architecture (ISA) to another. Accelerated binary translation (XBT) refers to BT using FPGA for hardware acceleration and feeding the target processor at-speed. This work proposes a reconfigurable pipelined structure built on FPGA that performs XBT on different ISAs. An XBT system that translates MIPS to RISC-V is implemented and tested on the Xilinx Zynq platform. Results of several benchmarks show obvious speedup of approximately 48 times compared to an equivalent software approach.
Christos Papachristou, PhD (Advisor)
Daniel Saab, PhD (Committee Member)
Seyed Hossein Miri Lavasani, PhD (Committee Member)

Recommended Citations

Citations

  • Chai, K. (2021). XBT: FPGA Accelerated Binary Translation [Master's thesis, Case Western Reserve University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=case1626692665154349

    APA Style (7th edition)

  • Chai, Ke. XBT: FPGA Accelerated Binary Translation. 2021. Case Western Reserve University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=case1626692665154349.

    MLA Style (8th edition)

  • Chai, Ke. "XBT: FPGA Accelerated Binary Translation." Master's thesis, Case Western Reserve University, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=case1626692665154349

    Chicago Manual of Style (17th edition)