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Hua_Chen_Thesis_Final - final format approved LW 12-4-15.pdf (1.23 MB)
ETD Abstract Container
Abstract Header
FPGA Based Multi-core Architectures for Deep Learning Networks
Author Info
Chen, Hua
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091
Abstract Details
Year and Degree
2015, Master of Science (M.S.), University of Dayton, Electrical Engineering.
Abstract
Deep learning a large scalable network architecture based on neural network. It is currently an extremely active research area in machine learning and pattern recognition society. They have diverse uses including pattern recognition, signal processing, image processing, image compression, classification of remote sensing data, and big data processing. Interest in specialized architectures for accelerating deep learning networks has increased significantly because of their ability to reduce power, increase performance, and allow fault tolerant computing. Specialized neuromorphic architectures could provide high performance at extreme low powers for these applications. This thesis concentrates on the implementation of multi-core neuromorphic network architecture on FPGA. Hardware prototyping of wormhole router unit is developed to control transmission of data packets running through between cores. Router units connect multiple cores into a large scalable network. This network is programmed on a Stratix IV FPGA board. Additionally, a memory initialization system is design inside the core to realize external network configuration. In this approaching, different applications could be mapped on the network without repeating FPGA compilation. One application called Image Edge Detection is mapped on the network. Finally this network outputs the desired image and demonstrate 3.4x run time efficiency and 3.6x energy-delay efficiency by FPGA implementation.
Committee
Tarek Taha, Dr. (Advisor)
Pages
54 p.
Subject Headings
Electrical Engineering
Keywords
Deep learning network
;
FPGA
;
neuromorphic processor
;
Wormhole router
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Citations
Chen, H. (2015).
FPGA Based Multi-core Architectures for Deep Learning Networks
[Master's thesis, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091
APA Style (7th edition)
Chen, Hua.
FPGA Based Multi-core Architectures for Deep Learning Networks.
2015. University of Dayton, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091.
MLA Style (8th edition)
Chen, Hua. "FPGA Based Multi-core Architectures for Deep Learning Networks." Master's thesis, University of Dayton, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449417091
Chicago Manual of Style (17th edition)
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Document number:
dayton1449417091
Download Count:
4,018
Copyright Info
© 2015, all rights reserved.
This open access ETD is published by University of Dayton and OhioLINK.