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FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor

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2015, Master of Science (M.S.), University of Dayton, Electrical Engineering.
The interest in specialized neuromorphic computing architectures has been increasing recently, and several applications have been shown to be capable of being accelerated on such platforms. This thesis describes the implementation of multicore digital neuromorphic processing systems on FPGAs. Static and Dynamic routing were used to allow communication between the cores on the FPGA. Several applications were mapped to the system including image edge detection, MNIST image classification, and biometric ECG classification. Given that all the applications were implemented on the same processor (hence same base Verilog code), with only a change in the synaptic weights and number of neurons utilized, the system has the capability to accelerate a broad range of applications.
Tarek Taha (Committee Chair)
Vijayan Asari (Committee Member)
Eric Balster (Committee Member)
42 p.

Recommended Citations

Citations

  • Qi, Y. (2015). FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor [Master's thesis, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140

    APA Style (7th edition)

  • Qi, Yangjie. FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor. 2015. University of Dayton, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140.

    MLA Style (8th edition)

  • Qi, Yangjie. "FPGA Based High Throughput Low Power Multi-core Neuromorphic Processor." Master's thesis, University of Dayton, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1449526140

    Chicago Manual of Style (17th edition)