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Netlist Security Algorithm Acceleration Using OpenCL on FPGAs

Pelini, Nicholas Michael
http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045

Abstract Details

2017, Master of Science in Computer Engineering, University of Dayton, Electrical and Computer Engineering.
Integrated circuits continue to grow in number of transistors and design complexity. Production of many of these components are also outsourced to facilities in a number of countries. Therefore, there is a need to ensure all parts within a system are reliable and free from modification. Verification tools must be able to assess circuits down to a gate level but also be scalable to assess complex designs. In response to this problem, an accelerated version of the Integrated Circuit Verification Software is proposed to determine if a manufacturer design is the same as a known, reference design by comparing the two netlists. Optimizations are made to the Python code, and an FPGA hardware accelerated version of the code is created using OpenCL. Results of the OpenCL implementation show an 18x to 24x speedup across various netlists. Additionally, a netlist previously too large for verification tools to run is able to be tested by the OpenCL algorithm.
Eric Balster (Advisor)
Frank Scarpino (Committee Member)
John Weber (Committee Member)
44 p.
Computer Engineering; Electrical Engineering
OpenCL; netlist; FPGA; DFF; verification; security; Python; gate; ctypes; fan in; fan out; flatten; hash; integrated circuit; acceleration; speedup

Recommended Citations

Citations

  • Pelini, N. M. (2017). Netlist Security Algorithm Acceleration Using OpenCL on FPGAs [Master's thesis, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045

    APA Style (7th edition)

  • Pelini, Nicholas. Netlist Security Algorithm Acceleration Using OpenCL on FPGAs. 2017. University of Dayton, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045.

    MLA Style (8th edition)

  • Pelini, Nicholas. "Netlist Security Algorithm Acceleration Using OpenCL on FPGAs." Master's thesis, University of Dayton, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1501861339318045

    Chicago Manual of Style (17th edition)

dayton1501861339318045
239
© 2017, all rights reserved.
This open access ETD is published by University of Dayton and OhioLINK.