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An Optimized Fixed-Point Synthetic Aperture Radar Back Projection Algorithm Implemented on a Field-Programmable Gate Array

Hettiarachchi, Don Lahiru Nirmal Manikka
http://orcid.org/0000-0002-6685-7221
http://rave.ohiolink.edu/etdc/view?acc_num=dayton16396566729522

Abstract Details

2021, Doctor of Philosophy (Ph.D.), University of Dayton, Engineering.
Time-domain back projection (BP) is a widely known method used in Synthetic Aperture Radar (SAR) image formation. Despite its advantages over other image formation algorithms, the BP method is hindered due to its computational complexity and its requirement of higher number of operations and processing power. Recently, Field Programmable Gate Array (FPGA) devices have been used for BP acceleration mainly due to their parallel processing capabilities, reconfigurability, scalability, and low power requirement. This dissertation presents a new SAR BP algorithm that is tested on a CPU to test the acceleration and functionality and compared with a traditional floating-point based SAR BP algorithm. It is shown that fixed-point based BP algorithm is faster than traditional algorithm and it maintains a high output image quality. The proposed BP algorithm process images with 15.69% speedup on average, while maintaining high quality image outputs. Recently, Intel introduced the Arria 10 FPGA which is the industry’s first FPGA that includes single-precision hardened Floating-Point Units (FPUs) on DSP blocks. With the advent of hardened floating-point, FPGA designers have largely abandoned fixed-point processing. Therefore, a series of arithmetic tests are created to evaluate whether fixed-point processing is obsolete considering the FPGA performance. A performance metric is developed to calculate the FPGA performance in terms of logic utilization and kernel speed. All programs are tested with Intel Stratix V FPGA which does not have hardened FPUs and Intel Arria 10 FPGA for comparison. The performance metric indicates that, on average, there is a 20.18% performance increase when Stratix V processes fixed-point operations and 27.17% performance increase when Arria 10 processes fixed-point operations. Even with hardened FPUs, it is shown that the Arria 10 FPGA exhibits a significant logic reduction when processing fixed-point operations. The results clearly indicate that the FPGAs perform better when processing converted fixed-point arithmetic operations compared to floating-point arithmetic regardless of whether they include hardened FPUs. A new Fixed-point based BP (FxBP) design for FPGA devices and a Floating-point based BP (FlBP) design are developed to compare performance. Both designs are developed with N-Dimensional Range (NDR) structure and Single Work Item (SWI) structure using OpenCL. The FPGA performance is evaluated using a FPGA performance metric (FPM). It is shown that FxBP-NDR and FxBP-SWI designs generate high quality back projected images compared to FlBP designs, while saving 16.87% and 42.54% on logic resources and gaining 17.90% and 91.62% on FPGA performance in NDR and SWI, respectively. Obtained results clearly indicate that FPGA devices perform significantly better with FxBP designs compared to FlBP designs, even with hardened FPUs. A series of optimization steps are applied to the FxBP-SWI design to address loop-carried dependencies, increase memory access efficiency, test different types of global memory, and test compiler optimization flags. Optimization tests are evaluated using kernel processing time (ms), throughput (MBps), and kernel fMAX. It is shown that the final optimized FxBP-SWI design has a 161.88% improvement in kernel processing time, a 61.77% improvement in throughput, and a 3.35% improvement in kernel fMAX compared to the reference FxBP-SWI design. Finally, optimized FxBP-SWI designs on a FPGA are compared with a FlBP-NDR design on a GPU. The total energy consumed over time (Watt-hour) is used to evaluate FPGA and GPU performances. It is shown that the final optimized FxBP-SWI designs’ total energy consumption over time (Watt-hour) is 41.49% less compared to the FlBP-NDR design on a GPU.
Eric Balster, Ph.D. (Advisor)
Tarek Taha, Ph.D. (Committee Member)
Russell Hardie, Ph.D. (Committee Member)
Muhammad Islam, Ph.D. (Committee Member)
129 p.
Electrical Engineering
Synthetic Aperture Radar; SAR, SAR image formation; Back projection algorithm; Fixed-point based design; FxBP; FxBP-SWI; Floating-point based design; Field Programmable Gate Array; FPGA; Stratix V; Arria 10; Stratix 10; OpenCL; Total energy consumption; FPGA vs. GPU; Hardened floating-point units; FPGAperformance metric

Recommended Citations

Citations

  • Hettiarachchi, D. L. N. M. (2021). An Optimized Fixed-Point Synthetic Aperture Radar Back Projection Algorithm Implemented on a Field-Programmable Gate Array [Doctoral dissertation, University of Dayton]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=dayton16396566729522

    APA Style (7th edition)

  • Hettiarachchi, Don Lahiru Nirmal. An Optimized Fixed-Point Synthetic Aperture Radar Back Projection Algorithm Implemented on a Field-Programmable Gate Array. 2021. University of Dayton, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=dayton16396566729522.

    MLA Style (8th edition)

  • Hettiarachchi, Don Lahiru Nirmal. "An Optimized Fixed-Point Synthetic Aperture Radar Back Projection Algorithm Implemented on a Field-Programmable Gate Array." Doctoral dissertation, University of Dayton, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=dayton16396566729522

    Chicago Manual of Style (17th edition)

dayton16396566729522
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This open access ETD is published by University of Dayton and OhioLINK.