As the scaling of MOSFET into sub-100nm regime, silicon-on-insulator (SOI) and double-gate (DG) MOSFET are expect to replace traditional bulk MOSFET. These novel MOSFET devices will be strong contenders for RF applications in wireless communications market. Of all the figure of merits for RF design, this work is concerned about the linearity design of bulk, single-gate SOI and DG SOI MOSFET in a comparative manner. By using ISE TCAD suite, 2D device simulations are conducted to analyze the influences of different physical mechanisms on linearity including quantum mechanics, non-equilibrium transport, impact ionization and self-heating effects. Then, influences of gate length scaling, silicon body thickness scaling and device sidewall scaling on linearity performance are investigated. In general, this work studies linearity performance of novel SOI MOSFET devices in terms of device physics and scaling effects with the hope of giving guidance to SOI MOSFET designers for high RF linearity design.