This research presents such new circuit simulation strategies and techniques as piecewise device modeling, circuit partitioning and event-driven analysis for fast simulation of analog MOS-based VLSI circuits. An automatic circuit formulation algorithm: based on the modified nodal analysis, and numerical analysis techniques such as Katzenelson algorithm and Gaussian elimination were combined with the proposed methods to form a complete solution for fast analog VLSI time domain simulation.
In order to verify and evaluate the proposed circuit simulation techniques and its partition strategies, a new circuit simulator, SAMOC, was built in the form of a digital computer program. This work presents details of building this circuit simulator with its data structure for circuit representation, and circuit block analysis scheduling for event-driven simulation. Both are specially designed for analyzing large scale MOS circuits on resource limited computer systems.
Simulations of several well-known small analog and digital circuits were presented for functional verification of SAMOC. A set of benchmark circuits which contain large amount of MOS transistors were used to evaluate the simulation efficiency improvement of the proposed methods comparing with standard industrial SPICE simulation. The simulation results indicate that SAMOC can exploit the latency of circuits, speed up the circuit simulation, and analyze such large circuits, which SPICE3f5 failed to do.