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ETD Abstract Container

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Scan path design of PLA to improve its testability in VLSI realization

Chiang, Kang-Chung
http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183128113

Abstract Details

1986, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).

Scan path design of PLA to improve its testability in VLSI realization

Janusz Starzyk (Advisor)
176 p.
Scan Path Design; PLA to Improve Testability; VLSI Realization

Recommended Citations

Citations

  • Chiang, K.-C. (1986). Scan path design of PLA to improve its testability in VLSI realization [Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183128113

    APA Style (7th edition)

  • Chiang, Kang-Chung. Scan path design of PLA to improve its testability in VLSI realization. 1986. Ohio University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183128113.

    MLA Style (8th edition)

  • Chiang, Kang-Chung. "Scan path design of PLA to improve its testability in VLSI realization." Master's thesis, Ohio University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183128113

    Chicago Manual of Style (17th edition)

ohiou1183128113
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© 1986, all rights reserved.
This open access ETD is published by Ohio University and OhioLINK.