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An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University

Lee, Hoon-Kyeu

Abstract Details

1986, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).

An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University

Janusz Starzyk (Advisor)
166 p.

Recommended Citations

Citations

  • Lee, H.-K. (1986). An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University [Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183139647

    APA Style (7th edition)

  • Lee, Hoon-Kyeu. An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University. 1986. Ohio University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183139647.

    MLA Style (8th edition)

  • Lee, Hoon-Kyeu. "An automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio University." Master's thesis, Ohio University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1183139647

    Chicago Manual of Style (17th edition)