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Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs

Ting, Darwin Ta-Yueh

Abstract Details

2008, Master of Science (MS), Ohio University, Electrical Engineering (Engineering and Technology).

The physical dimensions of bulk MOSFETs have been aggressively scaled down and these conventional devices will soon be experiencing limited improvements due to the scaling down. In order to continue performance improvements, new device architectures are needed. As a result, the double-gate (DG) MOSFET based on silicon-on-insulator (SOI) substrates has become a promising candidate for sub-40nm technology nodes. DG-MOSFET devices provide better control of threshold voltage by utilizing electrostatic coupling from two gates on either side of the channel. The DG-MOSFET also provides superior transconductance that is not only suitable for digital applications, but also is a strong competitor for analog and radio frequency (RF) applications.

Reconfigurable static and dynamic Boolean logic gates, as well as threshold logic gates designed with DG-MOSFETs, are proposed and analyzed in this thesis. All circuits are verified and performances are analyzed using the SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator. For reconfiguration in these circuits, a systematic back-gate biasing approach is utilized.

In this study, novel static, dynamic and reconfigurable threshold logic gates based on DG-MOSFETs are explored. Multiple functions are obtained on a single Boolean static logic circuit built with DG-MOSFETs. Alternatively, reduction of transistor usage on Boolean static and dynamic logic circuits is also built with DG-MOSFETs. Furthermore, improved threshold logic gates up to 12 inputs are designed, and their performances are investigated. The proposed threshold logic gates are not only compact but also have a wide range of functionality, due to programmable weights and logic threshold. A variety of current and voltage mode threshold logic gates implemented in DG-MOSFETs are simulated and analyzed, and their performances are compared with bulk and SOI MOSFET technologies. DG-MOSFETs exhibit great potential for flexible functionality and reconfiguration without losing any performance over SOI counterparts.

Savas Kaya (Advisor)
Janusz Starzyk (Committee Member)
Ralph Whaley (Committee Member)
Eric Stinaff (Committee Member)
110 p.

Recommended Citations

Citations

  • Ting, D. T.-Y. (2008). Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs [Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300

    APA Style (7th edition)

  • Ting, Darwin. Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs. 2008. Ohio University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300.

    MLA Style (8th edition)

  • Ting, Darwin. "Reconfigurable Threshold Logic Gates Implemented in Nanoscale Double-Gate MOSFETs." Master's thesis, Ohio University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1219672300

    Chicago Manual of Style (17th edition)