Low-density parity-check (LDPC) codes can approach the Shannon limit performance closely, and are becoming one of the most promising channel codes in the Error Control Coding area. The performance of an LDPC code with given length is mainly affected by the sizes of some combinatorial characteristics of its corresponding bipartite graph and the distribution of variable degrees and check node degrees. With the help of the density evolution algorithm, randomly designed LDPC codes, with carefully chosen degree distribution pairs, have been shown to achieve better Shannon capacity performance than their regular counterparts when decoded using the iterative belief propagation (BP) decoding algorithm. However, regular LDPC codes outperform their irregular counterparts in term of their error floors. Therefore, construction of LDPC codes which have both attractive error rate performance and low error floor performance has become an attractive topic.
Currently, optimization of variable node degree distribution and check node degree distribution for an LDPC code with given length, which could help the code to achieve good Shannon limit performance, has been extensively studied. In this dissertation, we demonstrate some approaches of improving the error floor performance for a given LDPC code with desired degree distribution pair. The contribution mainly includes three parts. In the first part, the relationship between cycles and unfavorable combinatorial characteristics (or trapping set for codes over AWGN channels and stopping set for codes over BEC channels) of LDPC codes is analyzed. The analysis indicates that large girths of LDPC codes could lead to low error floors. Based on this analysis, an approach of designing any individual irregular LDPC code with girth of six is proposed. The second part presents a novel algorithm of enumerating the worst unfavorable combinatorial characteristics with the help of building a searching tree. With the help of the enumeration results of this novel algorithm, the worst unfavorable combinatorial characteristics can be eliminated by refining the parity-check matrices of LDPC codes, which results in the improvement of the error floor performance of LDPC codes based on our simulation results. The above mentioned methods focus on designing LDPC codes with low error floors from the encoder side of the LDPC codes. Another possible approach of lowering the error floors is from the decoder side, which is studied in the third part of this dissertation. In the third part, the trapping sets of LDPC codes are extensively analyzed and a concept of pseudo-cycle is proposed. Based on the analysis, we present an improved decoder, a two-stage decoder, for LDPC codes to enable dealing with the negative influence caused by those unfavorable combinatorial properties of LDPC codes. The simulation results show that the error floors of LDPC codes can be lowered by more than one order of magnitude.
Unlike the current methods for lowering the error floors of LDPC codes, all the approaches proposed in this dissertation can be applied to any individual LDPC code. Based on our simulation results, these approaches can effectively decrease the error
floors for any specific LDPC code.