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Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning

Clark, Mark A
http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566

Abstract Details

2019, Master of Science (MS), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).
Network-on-chip (NoC) continues to be the preferred communication fabric in multicore and manycore architectures as the NoC seamlessly blends the resource efficiency of the bus with the parallelization of the crossbar. However, without adaptable power management the NoC suffers from excessive static power consumption at higher core counts. Static power consumption will increase proportionally as the size of the NoC increases to accommodate higher core counts in the future. NoC also suffers from excessive dynamic energy as traffic loads fluctuate throughout the execution of an application. Power-gating (PG) and Dynamic Voltage and Frequency Scaling (DVFS) are two highly effective techniques proposed in literature to reduce static power and dynamic energy in the NoC respectively. DVFS is a popular technique that allows dynamic energy to be saved but may potentially lead to a loss in throughput. Power-gating allows static power to be saved but can introduce new problems incurred by isolating network routers. Further complications include the introduction of long wake-up delays and break-even times. However, both DVFS and power-gating are critical for realizing energy proportional computing as core counts race into the hundreds for multi-cores. In this thesis, we propose two distinct but related techniques that enable energy proportional computing for NoC. We first propose LEAD - Learning-enabled Energy Aware Dynamic voltage/frequency scaling for NoC architectures. LEAD applies machine learning (ML) techniques to enable improvements in both energy and performance with reduced overhead cost. This allows LEAD to enact a proactive energy management strategy that relies on an offline trained regression model while also providing a wide variety of voltage/frequency (VF) pairs. In this work, we will refer to various VF pairs as modes. LEAD groups each router and the router’s outgoing links locally into the same V/F domain allowing energy management at a finer granularity without additional timing complications and overhead. We then build on LEAD and propose DozzNoC, an adaptable power management technique that effectively combines LEAD with a partially non-blocking power-gating technique. This allows DozzNoC to target both static power and dynamic energy simultaneously, thereby enabling energy proportional computing. Our ML DVFS techniques from LEAD are applied on top of a partially non-blocking power-gated scheme that uses real valued wake up/switching delays. DozzNoC also allows independently power-gated or voltage scaled routers such that each router and its outgoing links share the same voltage/frequency domain. We evaluate both LEAD and DozzNoC using trace files generated from PARSEC 2.1 and Splash-2 benchmark suits. Trace files are gathered at various network sizes and across two different network topologies. For a 64 core 4 × 4 concentrated mesh (CMesh) network, simulation results show that LEAD can achieve an average of 17% dynamic energy savings for an average loss of only 4% throughput. Our simulation results for DozzNoC on an 8 × 8 mesh network show that for an average decrease of 7% in throughput, we can achieve an average dynamic energy savings of 25% and an average static power reduction of 53%.
Avinash Karanth (Advisor)
Razvan Bunescu (Committee Member)
Savas Kaya (Committee Member)
90 p.
Computer Engineering; Electrical Engineering
Network-on-Chip; Machine Learning; Power-Gating; Energy Management for NoC; Machine Learning enhanced DVFS; Dynamic Voltage and Frequency Scaling;

Recommended Citations

Citations

  • Clark, M. A. (2019). Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning [Master's thesis, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566

    APA Style (7th edition)

  • Clark, Mark. Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning. 2019. Ohio University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566.

    MLA Style (8th edition)

  • Clark, Mark. "Dynamic Voltage/Frequency Scaling and Power-Gating of Network-on-Chip with Machine Learning." Master's thesis, Ohio University, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1544105215810566

    Chicago Manual of Style (17th edition)

ohiou1544105215810566
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© 2019, all rights reserved.
This open access ETD is published by Ohio University and OhioLINK.