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Hardware Security Threat and Mitigation Techniques for Network-on-Chips

Boraten, Travis Henry
http://orcid.org/0000-0002-1627-7069
http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1596031630118173

Abstract Details

2020, Doctor of Philosophy (PhD), Ohio University, Electrical Engineering & Computer Science (Engineering and Technology).
Today, hardware security for state-of-the-art integrated circuits (ICs) is a growing concern because semi-conductor supply-chains are increasingly complex and the industry is shifting to third-party fabrication plants on the global market. While the globalization of the semi-conductor industry allows for cutting cost, it opens the door for adversarial governments to steal intellectual property (IP), produce clones, counterfeits, and maliciously alter designs during the fabrication process. Since Network-on-Chip (NoC) architectures handle all communication between cores on-and-off chip, NoCs are one of the many likely targets attackers may try to compromise in future Multi-Processor System-on-Chips (MPSoCs). In this dissertation I propose a comprehensive set of threat detection and mitigation techniques to enhance the reliability NoC data-paths, control-paths, and application flows so that they can localize threats and gracefully degrade performance until they can be replaced. Specifically, I will show how to (1) overcome maliciously injected faults on links intended to compromise data integrity and induce Denial-of-Service attacks (securing data-paths), (2) identify security points-of-interest within the router micro-architecture and design Secure Model Checkers (SMCs) to validate functional correctness of those interest and prevent malicious gaming of resources in a compromised NoC (securing control-paths), and (3) to use Non-interference Based Routing (NIBR) to prevent network traffic induced side-channels (securing application flows). In my evaluation, I will show that the proposed Target-Activated Sequential-Payload (TASP) hardware trojans are cable of inducing a Denial-of-Service (DoS) attack and deadlocking a NoC within a few thousand cycles. To circumvent TASP and any other snooping 4 link HT, my proposed threat detector and switch-to-switch (s2s) obfuscation units allow for continual use of links instead of rerouting around them with only a 1-3 cycle performance penalty. The cost of mitigation is limited to an additional 2% in area overhead and 6% excess power consumption in the router micro-architecture. For HTs in the router micro-architecture logic, I identified 10 additional invariant rules over the existing 32 rules identified by [1]. These rules are enforced using SMCs with near instantaneous detection and provide greater threat coverage as SMCs now have access to state information in each router stage, not just the current stage. SMCs are capable of enhancing the security of control logic with only a 1.1% and 1.5% additional total router area overhead and power consumption respectively. Finally, with NIBR, I will show that routing on-demand coupled with reverse priority throttling can be used to prevent interference leaking information to the low domain and sustain performance in the high domain instead of reducing it. While prior work has shown to successfully prevent interference, most techniques do so at the cost of performance. I will show that NIBR improves performance by 2-20% over existing techniques with only a 1.84% power consumption penalty. By combining each of these approaches, NoCs can improve security on data-paths, control-paths, and application flows.
Avinash Karanth (Advisor)
Savas Kaya (Committee Member)
Jeffrey Dill (Committee Member)
Frank Drews (Committee Member)
Eric Stinaff (Committee Member)
David Ingram (Committee Member)
125 p.
Computer Engineering; Electrical Engineering
Network-on-Chip; Hardware Security; Hardware Trojans; Side-Channels; Denial-of-Service

Recommended Citations

Citations

  • Boraten, T. H. (2020). Hardware Security Threat and Mitigation Techniques for Network-on-Chips [Doctoral dissertation, Ohio University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1596031630118173

    APA Style (7th edition)

  • Boraten, Travis. Hardware Security Threat and Mitigation Techniques for Network-on-Chips. 2020. Ohio University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1596031630118173.

    MLA Style (8th edition)

  • Boraten, Travis. "Hardware Security Threat and Mitigation Techniques for Network-on-Chips." Doctoral dissertation, Ohio University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1596031630118173

    Chicago Manual of Style (17th edition)

ohiou1596031630118173
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This open access ETD is published by Ohio University and OhioLINK.