As communications and data processing equipments are being pushed to higher speeds and into the digital domain, it becomes necessary that they are complemented with the fastest analog to digital converters (ADC) possible. As device sizes scale down, more transistors can be fabricated in the same area, but also this requires a higher amount of heat dissipation in a smaller area. Also a lot of emphasis is being laid on designers to design products that consume less power as a step towards green computing and prevention of global warming. A result of all these needs is the requirement for a high speed, low power, high performance ADC. This requirement can be satisfied only with innovation and new techniques being developed.
In this thesis, a high speed flash sub-ranging ADC with digital speed and power control is developed. Two main innovations, current pumping and voltage pulling are developed and are applied to the components of the ADC. It is shown that these two techniques double the speed of the components. Further, it is shown how the speed and power of the components can be controlled digitally in addition to these techniques. This can be applied for the devices in case of stand-by and action modes. Further, digital control of the speed and power of the devices can be extended to be an option of the user.
The ADC has been developed targeting UWB applications and for memories, it is designed to perform with 6 bits resolution, at 2.5 Gsps at a single stage and targeting 2 stage time interleaving to work at 5 Gsps with 2 speed and power settings but extend able to N bits and N power and speed settings. Simulations are shown to support the theories developed.
The whole ADC has been developed using the 0.35u CMOS technology at transistor level implementation and with a 1.8 V supply to be compatible with 0.18u CMOS technology.
The chip is designed targeting cheap and widely available fabrication, it uses a single well process, 4 layers of metal and single layer of poly and relies on CMOS technology.