As VLSI processes scale down to keep up with digital demands, classical transistor models become less and less accurate reducing the ability to characterize transistors for use in analog design. Even with high accuracy models used for simulation such as BSIM4, it is still difficult for analog designers to gain that important insight into crucial I-V relationships of the devices that makes analog design possible. Deep submicron technologies require new design methods to take advantage of high-speed digital transistors for data acquisition. This thesis focuses on using computer-aided methodologies to gain insight into the design and characterization of sampling circuits.
In addition to suffering from higher-order effects due to technology scaling, sampling systems also must contend with other non-idealities. Effects such as aperture jitter in the sampling clock can affect the accuracy of a sampling circuit in the time-domain, and channel charge injection from MOSFET switches can cause input dependant hold steps on the output samples, affecting the signal in the frequency domain. This thesis also covers computer-aided analysis methods that can help designers comprehend and possibly mitigate these types of non-ideal effects on circuit performance.
A novel method for visually comparing signals with their ideal counterparts in the frequency domain is also introduced and explained. The goal for this type of analysis is to present an intuitive understanding of the frequency domain effects of circuit non-idealities, which could then be compensated for in the future in design and analysis.