Traditional ADCs (analog-to-digital converters) are built using analog circuitry that quantize the input signal in the voltage domain. As technology scales, voltage dynamic range decreases and design difficulties for analog circuits arise. Alternatively, time resolution is improving as technology scales. VCO (voltage controlled oscillator)-based quantizers are highly digital circuits which quantize in the time domain rather than in the voltage domain, and thus are becoming more attractive in deeply scaled technologies. The VCO converts an analog voltage into timing information that can then be quantized using digital circuitry.
Early work has used a simple digital counter to quantize the VCO signal. However issues with the counter “missing” VCO transitions near the sampling clock edge have led to the use of an FDC (frequency-to-digital converter) as the quantization circuit. The FDC has been widely adopted due to its inherent first order noise shaping characteristic. Another digital time quantization using TDCs (time-to-digital converters) have been traditionally used in PLLs to quantize the VCO phase error but have not been applied to VCO-based ADCs.
In this document, we propose for the first time the use of a TDC for time quantization in the VCO-based ADC. Both methods of using the TDC and the FDC are compared. While The SNR of the VCO-based quantizer using either the FDC or TDC is dependent on some common parameters such as VCO tuning range, Kv, x(t), and OSR (oversampling ratio), the TDC has two additional influences on the SNR; namely the VCO center frequency, fc, and buffer delay of the delay chain.
Both TDC and FDC based quantizers were examined in the presence of VCO nonlinearity, VCO phase noise, and sampling clock jitter. The comparison involves using the same baseline VCO and sampling clock. Modeling and analysis of the VCO-based quantizer and theoretical SNR calculations of the ideal VCO-based quantizers with and without non-idealities are presented.
The model results show that both FDC and TDC are impacted similarly when VCO nonlinearity and phase noise are introduced. However, when sampling clock jitter is introduced the FDCs SNR degrades significantly compared to the TDC. This can be attributed to the FDC losing its first order noise shaping response.
In summary this work presents an alternative method to using an FDC in a VCO-based quantizer which can achieve the same SNR performance with less sensitivity to sampling clock jitter.