The Linearization of power ampliers is a research area of growing importance. Among the many approaches which have been tried, digital predistortion (DPD)remain, one of the most promising techniques. In this thesis, a new generalized frequency-selective DPD technique is investigated. The proposed linearization algorithm is signal independent and any band limited signal can be linearized. 3rd and 5th order linearizations are demonstrated using various multi-tone signals. For 3rd order linearization, more than 15 dB cancellation for the inband distortion, 14 dB cancellation on 3rd order interband intermodulation distortion (IMD) were achieved. For the 5th order linearization, more than 15 dB IMD cancellation on inband, 16 dB cancellation on the 3rd order interband IMD, and 6 dB on 5th order interband IMD cancellation were achieved. To demonstrate the applicability of the algorithm to multiple bands, the two-band theory was modied to a three-band theory with up to 3rd order compensation. In the three-band case, the interband linearization played an important role in the overall performance. Without the interband linearization, only 3-4 dB IMD cancellation was observed. However, with interband compensation, more than 10 dB IMD cancellation was achieved. For the three-band case, to investigate the robustness of the DPD system, the middle channel was turned off and the same coefficients worked well for two bands.
In recent DPD applications, the linearization of largely spaced two-band signals have generated a lot of interest. In this work, the same algorithm was applied to 250 MHz spaced signal and more than 15 dB IMD cancellation was achieved. For the signal separation, a digital IF technique was proposed which uses only a single local oscillator (LO) for synthesizing the band separation. Previous works used two dierent LOs for the signal generation using expensive commercial synthesizers. In this work, a low cost testbed consisting of a field programmable gate arrays (FPGA) and two commercial upconverters is used.
For higher peak to average power ratio (PAPR) signal, a two-band crest factor reduction (CFR) block is proposed. MATLAB simulations and an subsequent FPGA implementation yield an excellent agreement on the performance with a 20 dB adjacent channel power ratio (ACPR) improvement achieved with 2.5 dB PAPR reduction.