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Auto-Determination of Cache/TLB parameters

Kommanaboina, Kishor Yadav

Abstract Details

2013, Master of Science, Ohio State University, Computer Science and Engineering.
Modern optimizing compilers are adept at performing transformations like loop tiling, fusion, etc. The improvement in performance achieved by compilers due to these transformations relies upon the assumptions made by the compilers about the properties of the different levels of caches and TLBs. Having accurate information about these hardware components can go a long way in helping the compiler generate efficient code. In this paper, We present a novel algorithm which relies on micro-benchmarks and repeated accesses to memory in fixed stride fashion to deduce the number of sets, the associativity and line-size of the different levels of caches and TLBs across different architectures. We compare our framework against other existing techniques and show the effectiveness of our approach across architectures. We show that the approaches previously developed are unable to differentiate between all levels of cache and in some cases are unable to detect the properties of different levels of TLB.
Sadayappan Ponnuswamy (Advisor)
48 p.

Recommended Citations

Citations

  • Kommanaboina, K. Y. (2013). Auto-Determination of Cache/TLB parameters [Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773

    APA Style (7th edition)

  • Kommanaboina, Kishor Yadav. Auto-Determination of Cache/TLB parameters. 2013. Ohio State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773.

    MLA Style (8th edition)

  • Kommanaboina, Kishor Yadav. "Auto-Determination of Cache/TLB parameters." Master's thesis, Ohio State University, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=osu1367581773

    Chicago Manual of Style (17th edition)