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An Investigation of Power Consumption for Fault-Tolerant Digital Circuits.pdf (590.88 KB)
ETD Abstract Container
Abstract Header
An Investigation of Power Consumption for Fault-Tolerant Digital Circuits
Author Info
Engelken, Corey M
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=osu1392155815
Abstract Details
Year and Degree
2014, Master of Science, Ohio State University, Electrical and Computer Engineering.
Abstract
Power consumption is an important aspect in electronic systems. Lowering the power consumption of the components in the system can increase the system’s energy efficiency and lower the heat dissipated to its surrounding area. FPGAs and CPLDs are devices found in electronic systems. Depending on the digital circuit programmed onto them, the current consumption may vary. If this is the case, then a new way to define the efficiency of a digital circuit is possible; one that includes the power consumed by the FPGA or CPLD. Fault-tolerant digital circuits that include error detection may be able to operate on a FPGA or CPLD at a lower supply voltage and decrease its power consumption. This thesis includes the preliminary and proof-of-concept work to show that devices do consume different amounts of power based on the digital circuit programmed onto them. Additionally, if fault-tolerant circuits are used, then the device can operate at a lower voltage and ultimately consume less power, even though the fault-tolerant digital circuit is larger and more complex. To fully test this idea, the current and power consumed by Altera MAX7000S chips will be measured while operating various circuits. The circuits used will be a 4-bit binary code counter, a 4-bit gray code counter and a dual-rail 4-bit gray code counter with error detection. It will be found that the binary code counter consumed more power than the gray code counter and that, at a voltage of approximately 4.8 V, the dual-rail gray code counter with error detection consumed less power than the standard 4-bit gray code counter.
Committee
Joanne DeGroat, Dr. (Advisor)
Villarroel Wladimiro, Dr. (Committee Member)
Pages
45 p.
Subject Headings
Computer Engineering
;
Electrical Engineering
;
Energy
;
Engineering
Keywords
Power Consumption
;
FPGA
;
CPLD
;
VHDL
;
Nominal Voltage
;
Fault-Tolerant
;
Fault-Tolerance
;
Digital Circuits
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Citations
Engelken, C. M. (2014).
An Investigation of Power Consumption for Fault-Tolerant Digital Circuits
[Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1392155815
APA Style (7th edition)
Engelken, Corey.
An Investigation of Power Consumption for Fault-Tolerant Digital Circuits.
2014. Ohio State University, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=osu1392155815.
MLA Style (8th edition)
Engelken, Corey. "An Investigation of Power Consumption for Fault-Tolerant Digital Circuits." Master's thesis, Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1392155815
Chicago Manual of Style (17th edition)
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Document number:
osu1392155815
Download Count:
525
Copyright Info
© 2014, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.