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Compiler Techniques for High Performance Computing, Energy Efficiency, and Resilience

Tavarageri, Sanket
http://rave.ohiolink.edu/etdc/view?acc_num=osu1397493916

Abstract Details

2014, Doctor of Philosophy, Ohio State University, Computer Science and Engineering.
The technology trends have brought parallel computers — multi-core and many-core processors to the mainstream. Parallel computing presents formidable challenges for compilers from performance and energy view-points: how to generate codes that achieve portable high performance on different processor architectures; how to support cache coherence for parallel processors at a reasonable hardware and energy cost etc. This dissertation develops solutions to both of the aforementioned questions — we propose novel adaptive tiling algorithms that enable dynamic change of tile sizes so that software can be adapted to different execution environments by altering tile sizes. Compiler techniques are developed for software cache coherence in order that expensive hardware cache coherence methods can be replaced or simplified to reduce energy and hardware expenditure associated with the task of providing cache coherence. The technology scaling has improved processor performance at a much faster rate than memory performance. As a result, current processor architectures incorporate large cache memories in an attempt to bridge the gap between computing and memory-access speeds (cache memories can fetch reused data much faster compared to main memory). This dissertation presents compiler techniques to tackle leakage (static) energy problem in cache memories. Compiler algorithms presented analyze data reuse pattern in application codes and derive the amount of cache that has to be kept on to not affect performance. The excessive cache capacity can be turned off to save leakage energy. The smaller technology feature sizes make hardware susceptible to transient faults. The implication for memory subsystem (including cache memories, main memory and datapath) is that high-energy particle strikes may cause bit-flips and hence, affect correctness of program results. In this dissertation, a compiler approach to introduce checksum computations in the application program is developed to detect memory errors. The techniques are light-weight in terms of performance and memory bandwidth requirements. In sum, the dissertation makes contributions to advance compiler technology to achieve high-performance for parallel applications, to reduce energy costs, and to effectively address transient hardware errors.
P Sadayappan (Advisor)
Atanas Rountev (Committee Member)
Paul Sivilotti (Committee Member)
188 p.
Computer Science

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Citations

  • Tavarageri, S. (2014). Compiler Techniques for High Performance Computing, Energy Efficiency, and Resilience [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1397493916

    APA Style (7th edition)

  • Tavarageri, Sanket. Compiler Techniques for High Performance Computing, Energy Efficiency, and Resilience. 2014. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1397493916.

    MLA Style (8th edition)

  • Tavarageri, Sanket. "Compiler Techniques for High Performance Computing, Energy Efficiency, and Resilience." Doctoral dissertation, Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1397493916

    Chicago Manual of Style (17th edition)

osu1397493916
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© 2014, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.