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Probabilistic approaches for verification of unlikely inserted errors in Hardware Description Languages

Pasupuleti, Venkata Sai Manoj
http://rave.ohiolink.edu/etdc/view?acc_num=osu1452182260

Abstract Details

2016, Master of Science, Ohio State University, Electrical and Computer Engineering.
With technology becoming more advanced each day and CMOS scaling being done proportionately to accommodate the size, speed and advancement in technology, more transistors are packed on to the same chip, thereby making fault tolerance, reliability and error detection an increasingly important design specification for processors. Unfortunately, for all practical purposes it is not possible to test the functionality of many digital integrated circuits chips exhaustively, since they can involve billions of components. Thus, there are no guarantees that all possible errors in the chip design and manufacture can be found. Therefore, random test vectors are usually generated which would help to test the functionality for most parts of the IC design. This leads to hardware being vulnerable to the insertion of malicious errors, similar to the problem of software viruses embedded into large software programs. Hence, in this thesis, prior and posteriori probabilities are developed to explore code in Hardware Description Language (HDL) designs of digital entities that are most vulnerable to errors. This thesis develops a probabilistic approach which is based on the assumption that lines of code with very low probabilities of execution are the best place to insert malicious errors, such as a Hardware Trojan. To explore this idea, two versions of 16bit ALU’s, one a Golden ALU (error Free) and second a Modified ALU (which has errors inserted into it) are used. From the designed ALU entities, the probability of execution of each ALU section is determined to be as follows P(AND-XOR) < P (AND-OR) < P (SUM-XOR) < P (SUM-OR) < P (No error loop).And the vulnerabilities associated with each of these loops was found to be (AND-XOR)> (AND-OR)> (SUM-XOR)> (SUM-OR)> (No-Error). By design, the exhaustive testing probabilities are derived as priori probabilities in this thesis. However, these results have been verified against posteriori probabilities for discrete finite test cases. The results showed that loops with low probability (e.g., SUM-XOR loop, has probabilities very close to 0.00013 are consistent in priori and posteriori values, while high probability loops (e.g., No-error, has probabilities around 0.99) are not. The recommendation section in this thesis outlines the next step to improve the result consistencies. These test vectors used on DUT had a Fault detection accuracy of 0.8, with scope of improvement.
Steven Bibyk (Advisor)
Wladimiro Villarroel (Committee Member)
85 p.
Computer Engineering; Electrical Engineering

Recommended Citations

Citations

  • Pasupuleti, V. S. M. (2016). Probabilistic approaches for verification of unlikely inserted errors in Hardware Description Languages [Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1452182260

    APA Style (7th edition)

  • Pasupuleti, Venkata Sai Manoj. Probabilistic approaches for verification of unlikely inserted errors in Hardware Description Languages. 2016. Ohio State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1452182260.

    MLA Style (8th edition)

  • Pasupuleti, Venkata Sai Manoj. "Probabilistic approaches for verification of unlikely inserted errors in Hardware Description Languages." Master's thesis, Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1452182260

    Chicago Manual of Style (17th edition)

osu1452182260
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This open access ETD is published by The Ohio State University and OhioLINK.