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Dinesh Ravikumar MS Thesis.pdf (2.74 MB)

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Modeling of Ideal and Error Characteristics of a Multi – Stage, Time Interleaved Sub – Ranging Analog to Digital Converter using MATLAB.

Ravikumar, Dinesh
http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228

Abstract Details

2016, Master of Science, Ohio State University, Electrical and Computer Engineering.
High Speed Analog to Digital Converters (ADCs) are being widely used in digital communication, digital oscilloscopes and fast data acquisition systems since they provide the best dynamic performance in high frequency and wide bandwidth applications. The design of these high speed converters pushes the dynamic limits of the individual components beyond the basic data converters, incorporating techniques such as interleaving, averaging and dithering. This along with the requirements of low power consumption, smaller chip areas and high sampling rates which are contradictory to the high accuracy requirements, have led to the rise of complex architectures of these converters. Therefore Conceptual modeling of these converter architectures are of prime importance to gain insights on the various challenges and errors that one might come across during the actual design for a specific application. This Master’s thesis focuses on modeling a high speed time interleaved sub-ranging ADC using MATLAB programming tool. The ADC modeled has 8 time interleaved 12 bit 3 stage pipelined architecture with one bit overlap. The INL and DNL characteristics of the modeled ADC under ideal and non-ideal conditions are investigated. The thesis studies estimation of two different types of ADC errors. The first type includes the static errors that could exist in an ADC like resistor mismatch, comparator reference offset and residual gain amplifier error etc. The second type includes temporal aspects of the converter like the impact of timing skew on time interleaving where several ADCs are operated in parallel.
Waleed Khalil, Dr (Advisor)
Ayman Fayed, Dr (Committee Member)
103 p.
Electrical Engineering
ADC Modeling

Recommended Citations

Citations

  • Ravikumar, D. (2016). Modeling of Ideal and Error Characteristics of a Multi – Stage, Time Interleaved Sub – Ranging Analog to Digital Converter using MATLAB. [Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228

    APA Style (7th edition)

  • Ravikumar, Dinesh. Modeling of Ideal and Error Characteristics of a Multi – Stage, Time Interleaved Sub – Ranging Analog to Digital Converter using MATLAB. 2016. Ohio State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228.

    MLA Style (8th edition)

  • Ravikumar, Dinesh. "Modeling of Ideal and Error Characteristics of a Multi – Stage, Time Interleaved Sub – Ranging Analog to Digital Converter using MATLAB." Master's thesis, Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1460971228

    Chicago Manual of Style (17th edition)

osu1460971228
3,411
© 2016, some rights reserved.Creative Commons License Modeling of Ideal and Error Characteristics of a Multi – Stage, Time Interleaved Sub – Ranging Analog to Digital Converter using MATLAB. by Dinesh Ravikumar is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by The Ohio State University and OhioLINK.