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Compensation and Calibration Techniques for High Performance Current-Steering DACs

McDonnell, Samantha
http://rave.ohiolink.edu/etdc/view?acc_num=osu1468060900

Abstract Details

2016, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
A myriad of research efforts, covering architectural, circuit and technological aspects, have been made towards improving the performance of digital-to-analog converters (DACs). However, the quest to achieve stringent dynamic linearity requirements (> 70dBc SFDR) over many gigahertz of bandwidth presents grand challenges to circuit designers and high-yield manufacturers. In light of these challenges, various calibration and compensation techniques have evolved over the past two decades to overcome design and process technology limitations. In this work, the sources of nonlinearity in current-steering DACs are described and common circuit techniques, along with device technologies, which enable a high-performance baseline DAC, are detailed. The effect of these non-idealities are investigated using a new modeling paradigm which accurately predicts the SFDR of the DAC in the presence of statistical process mismatch. This model offers a total speedup of ~330x per frequency point compared with Monte Carlo-based simulation methods. The model is useful in evaluating and developing calibration circuits, which is the focus of this work. To highlight prior art, a historical overview of compensation and calibration techniques is presented, outlining the shift from amplitude to timing and dynamic correction. Furthermore, several techniques are simulated using the DAC model to compare their efficacy. In addition, current and emerging architectures are described, which help extend the synthesizable bandwidth of the DAC. As operating frequency increases beyond several MHz, timing errors are detrimental to DAC performance, yet few timing calibration techniques have been developed and verified on chip. This highlights the need for a novel timing calibration technique. A new timing calibration, termed adaptive delay calibration (ACD), is designed in support of this work. It reduces timing mismatches in the DAC through modulation of the clock signal’s delay to the DAC retiming data latches. The proposed technique is shown to reduce the effect of timing mismatches and improve the SFDR for both a single DAC and time interleaved (TI) DAC, as well as improve the signal-to-image rejection ratio (SIRR) in the TI DAC. To verify the ACD technique, a 14-bit DAC operating at fclk=3GHz is designed in a 130nm BiCMOS process. The DAC includes amplitude calibration, dynamic compensation, and the proposed ACD technique. Overall, ACD calibration shows promising results, however, it was not able to be verified on chip due to unforeseen design issues. These issues are investigated and proposed solutions are provided.
Waleed Khalil (Advisor)
Steven Bibyk (Committee Member)
Joel Johnson (Committee Member)
133 p.
Engineering

Recommended Citations

Citations

  • McDonnell, S. (2016). Compensation and Calibration Techniques for High Performance Current-Steering DACs [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1468060900

    APA Style (7th edition)

  • McDonnell, Samantha. Compensation and Calibration Techniques for High Performance Current-Steering DACs. 2016. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1468060900.

    MLA Style (8th edition)

  • McDonnell, Samantha. "Compensation and Calibration Techniques for High Performance Current-Steering DACs." Doctoral dissertation, Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1468060900

    Chicago Manual of Style (17th edition)

osu1468060900
4,034
© 2016, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.