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Design of A Double-End Sourced Multi-Chip Power Module and A High Power-Density Three-Phase Inverter

Wang, Miao
http://rave.ohiolink.edu/etdc/view?acc_num=osu1479744941973868

Abstract Details

2016, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
The silicon carbide (SiC) MOSFET has been widely studied over the past decade due to its superior characteristics compared with the conventional silicon (Si) MOSFET. The SiC MOSFET significantly lowers switching losses with its fast switching speed, while its high-voltage blocking capability contributes to a large reduction in on-status resistance, which reduces power losses and improves the efficiency of the system. The capability to operate SiC devices at high temperatures greatly simplifies the thermal management of the system and increases the power density. Due to limitations in the current-handling capability of single bare dies, power modules—where multiple bare dies are put into small packaging to provide improved performances—are commonly adopted in high-current applications. The conventional power module packaging that is designed for Si devices, however, will degrade the performance of the SiC device and will limit the device from being fully utilized. For these reasons, the objective of this work is to achieve improved performance in multi-chip SiC MOSFET power modules. The contributions of this work may be summarized as follows: First, the study proposes an improved design for wire-bonded multi-chip SiC MOSFET power modules. The proposed structure, called a double-end sourced (DES) layout, adopts two pairs of DC bus terminals and sources the power module symmetrically from two ends. The structure provides each MOSFET in the module with two paralleled commutating loops and greatly reduces power-loop inductance. In addition, the symmetrical structure of the DES layout successfully mitigates the imbalance of the power loops between the parallel MOSFETs and allows for consistent performance of the power module. This study examines the performance of the proposed DES layout both in simulations and experiments and compares the proposed layout’s performance with that of a conventional baseline layout. During the double-pulse tests, the DES layout showed much lower voltage overshoot during the turn-off transient stage due to the layout’s reduced power-loop inductance. The dynamic-current sharing during the turn-on transient stage was also greatly improved because of the balanced power loops due to the DES layout. This improved switching performance contributes to lower and more evenly distributed power losses among the paralleled SiC MOSFETs, which improves the efficiency of the power module and makes the paralleled devices equally fully utilized. The study also evaluates the thermal performance of the power modules. In the simulation, for example, the DES layout demonstrated a more than 15 percent reduction in the size of the heatsink while maintaining the same highest junction temperature as the baseline layout; the temperature was also more evenly distributed within the power module. An experimental continuous power test was conducted in which the two layout modules were setup in the same full-bridge converter, with each module consisting of one half-bridge. The DES layout showed a much lower temperature increase compared with the baseline layout under the same operating conditions as well as a higher power-handling capability with the same temperature increases. The study’s second contribution is to propose a simplified circular-loop model for rapid estimation of the near-field radiation noise that is exhibited by the power module. In the study, the magnetic field was calculated on a measurement plane above the power module, which was then verified by experimental measurement using near-field probes and a spectrum analyzer. The DES layout was found to decrease the peak magnetic field level; more importantly, it generated less magnetic flux in the area in which the gate-driver board was placed. This indicates that the DES layout will lead to lower radiative interference to the power electronics in the layout’s surrounding environment. The work’s third contribution is to propose a three-phase inverter that accommodates this unique structure. The design ensures that each single-phase module is symmetrically sourced from the DC bus-bar. In addition, the design increases the compactness of the inverter system by incorporating a vertical-integrated DC link and sandwiching the gate-driver board between the DC bus-bar and the power modules. The power stage of this three-phase inverter weights ~705 grams and is successfully operated at 300 V DC input voltage with 0.85 modulation index and 70 A peak output current. This allowed the tested power density to attain up to 21.9 kVA/kg. Finally, the efficiency of the three-phase inverter was evaluated; it was found to attain a peak efficiency of 98.9 percent. In summary, this work presents a new layout for multi-chip SiC MOSFET power modules and demonstrates improved performance compared with conventional designs. A prototype of the three-phase inverter that adopts the DES layout power modules was built with a power density of 21.9 kVA/kg and 98.9 percent peak efficiency.
Longya Xu (Advisor)
Fang Luo (Advisor)
Jin Wang (Committee Member)
Rajendra Singh (Committee Member)
132 p.
Electrical Engineering

Recommended Citations

Citations

  • Wang, M. (2016). Design of A Double-End Sourced Multi-Chip Power Module and A High Power-Density Three-Phase Inverter [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1479744941973868

    APA Style (7th edition)

  • Wang, Miao. Design of A Double-End Sourced Multi-Chip Power Module and A High Power-Density Three-Phase Inverter. 2016. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1479744941973868.

    MLA Style (8th edition)

  • Wang, Miao. "Design of A Double-End Sourced Multi-Chip Power Module and A High Power-Density Three-Phase Inverter." Doctoral dissertation, Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1479744941973868

    Chicago Manual of Style (17th edition)

osu1479744941973868
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© 2016, some rights reserved.Creative Commons License Design of A Double-End Sourced Multi-Chip Power Module and A High Power-Density Three-Phase Inverter by Miao Wang is licensed under a Creative Commons Attribution-NonCommercial-NoDerivs 3.0 Unported License. Based on a work at etd.ohiolink.edu.
This open access ETD is published by The Ohio State University and OhioLINK.