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Development of Trust Metrics for Quantifying Design Integrity and Error Implementation Cost

Kimura, Adam
http://orcid.org/0000-0002-5141-2182
http://rave.ohiolink.edu/etdc/view?acc_num=osu1492607691591962

Abstract Details

2017, Doctor of Philosophy, Ohio State University, Electrical and Computer Engineering.
One of the major concerns in the Integrated Circuit (IC) industry today is the issue of Hardware Trust. This problem has risen as result of increased outsourcing and from the integration of more third party Intellectual Property (IP) into designs. Trusted Microelectronics is a new field of research that has emerged to address these hardware assurance concerns. Trojan Detection, Design for Security and Trust, Trusted Supply Chain Management, Anti-Counterfeiting, Trusted Design Verification, and Vulnerability & Attack Mitigation are the major sub-fields of Trusted Microelectronics where research progress is being made. There is; however, currently a lack of well-defined metrics for quantifying Hardware Trust. As such, developing a portfolio of Trust Metrics is a needed contribution in the Trusted Microelectronics space that will also bring value to the other sub-fields of Trust. In this work, a Trust Metric Solution Space is defined in order to establish a roadmap for developing Trust Metrics. The Solution Space also creates a coalescing point for the metrics work being conducted in other communities to integrate into. An Error Implementation Cost (EIC) measure is developed as a technique to quantify errors and to allow error ranking and rating. Four MIPS Processor test cases containing embedded errors are utilized in order to show that the EIC scoring can be applied for creating quantifiable differentiation between different errors of varying severity. Errors 1 and 2 were shown to be the least severe with System Payloads of 0.0181 and 0.0010 respectively. Errors 3 and 4 were shown to be more severe with System Payloads of 0.5140 and 0.3216 respectively. The EIC scoring is then used to assist in developing Test Articles (TA) for example case scenarios that contain embedded errors. A 32-bit Floating Point Adder, a Fixed to Floating Point Converter, a MIPS Processor, and a Full System TA was developed in order to apply the techniques for evaluating hardware integrity. The Design Integrity (DI) analysis parses the design out into five sub-domain profiles (Logical Equivalence, Power Consumption, Signal Activity Rate, Structural Architecture, and Functional Correctness) in order to track deviation away from its intended reference profile. The deviation measurements were unique to each domain on a [0, 1] scale and were aggregated together to produce a DI metric on a [0, 5] scale that can be correlated to Hardware Trust. The DI analysis was subjected to a more complex test article with embedded errors in order show the effectiveness of the DI analysis in quantifying integrity. The result of the analysis demonstrated how several different TAs of varying integrity could be quantitatively ranked with higher or lower Trust. TA0 had the highest Trust at 1.00/1.00 followed by TA3 and TA4, both at 0.88/1.00. TA1 had a measure of 0.65/1.00 and TA2 had the worst Trust at 0.59/1.00. A metric for Reference Quality is also proposed since the DI analysis hinges heavily on the utilization of design references. The Reference Quality metric is utilized in conjunction with the DI metric to arrive at a final Trust Measure Figure of Merit. Finally, future work and recommendations are made for continuing the progress this work has made. Recommendations for future work would involve exploring nonlinear distance measures to track deviation from the expected reference profile, as well as developing enough design cases to define a probabilistic model of Trust. Additional work could also be directed towards determining the non-uniformity of the Correlation Factor weighting of the aggregated domains and exploring new sub-domain profiles of Design Integrity. (NOTE: The Appendix including all developed code, designs, testbenches, scripts, etc. has not been approved for public release.)
Steve Bibyk, Dr. (Advisor)
Lisa Fiorentini, Dr. (Committee Member)
Ayman Fayed, Dr. (Committee Member)
149 p.
Electrical Engineering
hardware; trust; metrics; assurance; error; implementation; cost; design; integrity; FPGA; integrated; circuits; verification; formal; deviation; microelectronics

Recommended Citations

Citations

  • Kimura, A. (2017). Development of Trust Metrics for Quantifying Design Integrity and Error Implementation Cost [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492607691591962

    APA Style (7th edition)

  • Kimura, Adam. Development of Trust Metrics for Quantifying Design Integrity and Error Implementation Cost . 2017. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1492607691591962.

    MLA Style (8th edition)

  • Kimura, Adam. "Development of Trust Metrics for Quantifying Design Integrity and Error Implementation Cost ." Doctoral dissertation, Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492607691591962

    Chicago Manual of Style (17th edition)

osu1492607691591962
962
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This open access ETD is published by The Ohio State University and OhioLINK.