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Designing Future Low-Power and Secure Processors with Non-Volatile Memory

Pan, Xiang
http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669

Abstract Details

2017, Doctor of Philosophy, Ohio State University, Computer Science and Engineering.
Non-volatile memories such as Spin-Transfer Torque Random Access Memory (STT-RAM), Phase Change Memory (PCM), Resistive Random Access Memory (ReRAM), etc. are emerging as promising alternatives to DRAM and SRAM. These new memory technologies have many exciting characteristics such as non-volatility, high density, and near-zero leakage power. These features make them very good candidates for future processor designs in the power-hungry big data era. STT-RAM, a new generation of Magnetoresistive RAM, in particular is an attractive class of non-volatile memory because it has infinite write endurance, good compatibility with CMOS technology, fast read speed, and low read energy. With its good read performance and high endurance, it is feasible to replace SRAM structures on processor chips with STT-RAM. However, a significant drawback of STT-RAM is its higher write latency and energy compared to SRAM. This dissertation first presents several approaches to use STT-RAM for future low-power processor designs across two different computing environments (high voltage and low voltage). Overall our target is to take advantage of the benefits of STT-RAM over SRAM to save power and at the same time try the best to accommodate STT-RAM's write drawbacks with novel solutions. In high voltage computing environment, we present a low-power microprocessor framework -- NVSleep, that leverages STT-RAM to implement rapid checkpoint/wakeup of idle cores to save power. In low voltage computing environment, we propose an architecture - Respin, that consolidates the private caches of near-threshold cores into unified L1 instruction/data caches that use STT-RAM to save leakage power and improve performance. On top of this shared L1 cache design, we further propose a novel hardware virtualization core management mechanism to increase resource efficiency and save energy. Although the non-volatility feature of non-volatile memories can be leveraged to build power-efficient designs, it also brings in security concerns as data stored in these memories will be persistent even after system power-off. In order to address this potential security issue, this dissertation deeply studies the vulnerabilities of non-volatile memory as processor caches when exposed to "cold boot" attacks and then proposes an effective software-based countermeasure to eliminate this security threat with reasonable performance overhead.
Radu Teodorescu (Advisor)
Feng Qin (Committee Member)
Christopher Stewart (Committee Member)
Yinqian Zhang (Committee Member)
124 p.
Computer Engineering; Computer Science
Non-Volatile Memory, STT-RAM, Low-Power Processor Architecture, Cache, Near-Threshold Computing, Process Variation, Security, Secure Processor Design, Cold Boot Attack

Recommended Citations

Citations

  • Pan, X. (2017). Designing Future Low-Power and Secure Processors with Non-Volatile Memory [Doctoral dissertation, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669

    APA Style (7th edition)

  • Pan, Xiang. Designing Future Low-Power and Secure Processors with Non-Volatile Memory. 2017. Ohio State University, Doctoral dissertation. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669.

    MLA Style (8th edition)

  • Pan, Xiang. "Designing Future Low-Power and Secure Processors with Non-Volatile Memory." Doctoral dissertation, Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1492631536670669

    Chicago Manual of Style (17th edition)

osu1492631536670669
305
© 2017, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.