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Final thesis.pdf (1.31 MB)

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High speed Clock and Data Recovery Analysis

Namachivayam, Abishek
http://rave.ohiolink.edu/etdc/view?acc_num=osu1587583678200267

Abstract Details

2020, Master of Science, Ohio State University, Electrical and Computer Engineering.
Baud rate clock and data recovery circuits are critical to high speed serial links since these require only one sample per data period thereby requiring low speed samplers and comparators. This work models and discusses the backend of one particular Baud rate CDR – Mueller Muller, and analyses some of the building blocks of the CDR – Phase Detector, Phase Interpolator and the Quadrature Phase Generator. Firstly, a PAM-4 Quadrature Phase Detector operating at 80Gb/s is discussed. The challenges associated with designing a Mueller-Muller PD for an asymmetric channel are discussed and one way to resolve this issue is proposed. Then the underlying digital blocks that make up the Phase detector are expanded upon. Secondly, a 64-step digitally controlled Phase Interpolator running at 16GHz clock rate is analyzed and its design challenges with regards to achieving linearity and ensuring duty cycle fidelity are explored. Finally, a Quadrature Phase Generator with digital delay control is analyzed. It is modeled at 16GHz clock rate and the range/resolution problem and its impact on clock jitter is explored.
Tawfiq Musah (Advisor)
Ayman Fayed (Committee Member)
44 p.
Electrical Engineering
Mueller Mueller; Baud rate; Phase Detector; Unequalized CDR; Phase Interpolator; Quadrature generator; Phase Interpolation; PAM4; 4-way interleaved; CDR

Recommended Citations

Citations

  • Namachivayam, A. (2020). High speed Clock and Data Recovery Analysis [Master's thesis, Ohio State University]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587583678200267

    APA Style (7th edition)

  • Namachivayam, Abishek. High speed Clock and Data Recovery Analysis. 2020. Ohio State University, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=osu1587583678200267.

    MLA Style (8th edition)

  • Namachivayam, Abishek. "High speed Clock and Data Recovery Analysis." Master's thesis, Ohio State University, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1587583678200267

    Chicago Manual of Style (17th edition)

osu1587583678200267
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© 2020, all rights reserved.
This open access ETD is published by The Ohio State University and OhioLINK.