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Design, Implementation, and Test of Next Generation FPGAs Using Quantum-Dot Cellular Automata Technology

Raviraj, Tejas

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2011, Master of Science in Electrical Engineering, University of Toledo, College of Engineering.

Moore's Law states that the number of transistors on a unit area doubles every 18 months. Till date, CMOS technology has been successfully keeping pace with Moore‟s Law. However, it faces serious fundamental challenges in the future, and will soon reach a limit where the quantum effects will begin to dominate the device performance that make further scaling difficult. The International Technology Roadmap for Semiconductors (ITRS) predicts the size limit for CMOS technology to be limited in the range of 5 nm to 10 nm and believes this limit will be reached by 2017[1]. As the devices are exponentially scaled down various factors including power dissipation, gate leakage current, interconnection noise (introduction of crosstalk and hot electron effect) and stray capacitances will become potential bottlenecks to circuit performance. Thus, there is a pressing need for new technologies which can overcome these limitations more effectively. Researchers are investigating alternative technologies at the nano scale to replace CMOS technology in the future. Amongst the many technologies being investigated, Quantum-Dot Cellular Automata (QCA) is one promising transistor-less technology.

This research investigates the design, implementation, and simulation of a nano Field Programmable Gate Array (FPGA) using the Quantum-Dot Cellular Automata. The first phase of the research focuses on modeling, implementation, and simulation of a Configurable Logic Block (CLB) slice for a nano quantum FPGA. The proposed design is compared with various nano FPGA based architectures and optimized with respect to area and latency. The second phase of the research focuses on implementing a novel Built-In Self Test model at the quantum level for testing the CLB. New fabrication faults in the QCA components of the CLB are modeled and tested. Finally, the configurable logic block slices are tested by incorporating BIST in its design. The design is modeled using standard QCA cells with multiple layers for reliable interconnect crossovers. The design of the configurable logic block is implemented and simulated using the QCA Designer software tool.

Mohammed Y. Niamat, Dr. (Committee Chair)
Mansoor Alam, Dr. (Committee Member)
Ezzatollah Salari, Dr. (Committee Member)
151 p.

Recommended Citations

Citations

  • Raviraj, T. (2011). Design, Implementation, and Test of Next Generation FPGAs Using Quantum-Dot Cellular Automata Technology [Master's thesis, University of Toledo]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1302291185

    APA Style (7th edition)

  • Raviraj, Tejas. Design, Implementation, and Test of Next Generation FPGAs Using Quantum-Dot Cellular Automata Technology. 2011. University of Toledo, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=toledo1302291185.

    MLA Style (8th edition)

  • Raviraj, Tejas. "Design, Implementation, and Test of Next Generation FPGAs Using Quantum-Dot Cellular Automata Technology." Master's thesis, University of Toledo, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1302291185

    Chicago Manual of Style (17th edition)