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Design of A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm and Its Implementation

Guo, Xinyu
http://rave.ohiolink.edu/etdc/view?acc_num=toledo1338478834

Abstract Details

2012, Master of Science in Engineering, University of Toledo, College of Engineering.
A design of systolic array based Field Programmable Gate Array (FPGA) parallel architecture for Basic Local Alignment Search Tool (BLAST) Algorithm is proposed in the thesis. BLAST is a heuristic biological sequence alignment algorithm which has been used by bioinformatics experts. In contrast to other designs that detect at most one hit in one clock cycle, this design applies a Multiple Hits Detection Module which is a pipelining systolic array to search multiple hits in a single clock cycle. Further, A Hits Combination Block which combines overlapping hits from systolic array into one hit is proposed. These implementations completed the first step of BLAST architecture. After parallelizing the Ungapped Extension Blocks to accelerate the second step of BLAST, the new design in the thesis achieved better results than previously published architectures.
Hong Wang, PhD (Committee Chair)
Vijay Devabhaktuni, PhD (Committee Member)
Mansoor Alam, PhD (Committee Member)
71 p.
Bioinformatics; Computer Engineering; Computer Science
FPGA; Parallel; BLAST; Bioinformatics

Recommended Citations

Citations

  • Guo, X. (2012). Design of A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm and Its Implementation [Master's thesis, University of Toledo]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1338478834

    APA Style (7th edition)

  • Guo, Xinyu. Design of A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm and Its Implementation. 2012. University of Toledo, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=toledo1338478834.

    MLA Style (8th edition)

  • Guo, Xinyu. "Design of A Systolic Array-Based FPGA Parallel Architecture for the BLAST Algorithm and Its Implementation." Master's thesis, University of Toledo, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1338478834

    Chicago Manual of Style (17th edition)

toledo1338478834
977
© 2012, all rights reserved.
This open access ETD is published by University of Toledo and OhioLINK.