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Temperature Variation Effects on Asynchronous PUF Design using FPGAs

Gujja, Swetha
http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527

Abstract Details

2014, Master of Science, University of Toledo, Electrical Engineering.
A variety of logic circuits can be implemented on configurable platforms like Field Programmable Gate Arrays (FPGAs). FPGAs have attracted attention because of their usability over the last decade owing to their greater flexibility compared to full-Custom ICs and ASICs. With their growing popularity, FPGAs have become an attractive target for piracy and therefore, there is a need to develop techniques for their security. Integrated circuits are facing security issues like cloning, reverse engineering, overbuilding, and physical tampering. In order to overcome this challenge, the idea of Physical Unclonable Functions (PUFs) came into existence. PUFs are special challenge-response entities, embedded in a physical device and are used as hardware primitives in the field of hardware oriented security. PUFs extract secret keys from the unique physical characteristics of the chips, i.e., the manufacturing process variations in the chips, in order to authenticate an FPGA. In this thesis, a Self-Timed Ring Oscillator (STRO) based Asynchronous Physical Unclonable Function is implemented on an FPGA. Unlike synchronous ring oscillators, STROs use an asynchronous logic that eliminates the need for a global or centralized clock in its architecture. Synchronous circuits face challenges such as time closure effects, increasing clock rates, clock skews, and performance overhead, etc. The asynchronous logic employed in STROs overcomes these challenges. STROs act as building blocks for our proposed Asynchronous PUF design. In this design, the identically placed self-timed ring oscillators utilize the manufacturing process variations to obtain varying frequencies from the PUF. The output frequencies from STROs help in generating the response bits, which act as unique signatures to serve FPGA authentication, cryptographic key generation, and random number generation. The delay variation of interconnects and transistors on a chip is dependent on the junction temperatures, which could affect the response bits when there is a significant change in environmental temperatures. To determine the robustness, the proposed Asynchronous PUF design is validated by testing at 4 different locations on 13 FPGAs at different temperatures: room temperature, 0o C, 20o C, 45o C, and 70o C. At these temperatures, the frequencies are recorded and compared in order to generate the response bits. The uniqueness and reliability of the obtained responses are observed to be 48.04% (near to the desired 50%) and 97.66%, respectively. It is found that the reliability of the asynchronous design increases with increase in temperature.
Mohammed Niamat (Committee Chair)
Junghwan Kim (Committee Member)
Weiqing Sun (Committee Member)
123 p.
Electrical Engineering
PUFs, Hardware oriented security, Asynchronous Physical Unclonable Functions, uniqueness and reliability of PUFs, Temperature variation

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Citations

  • Gujja, S. (2014). Temperature Variation Effects on Asynchronous PUF Design using FPGAs [Master's thesis, University of Toledo]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527

    APA Style (7th edition)

  • Gujja, Swetha. Temperature Variation Effects on Asynchronous PUF Design using FPGAs. 2014. University of Toledo, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527.

    MLA Style (8th edition)

  • Gujja, Swetha. "Temperature Variation Effects on Asynchronous PUF Design using FPGAs." Master's thesis, University of Toledo, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1417716527

    Chicago Manual of Style (17th edition)

toledo1417716527
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This open access ETD is published by University of Toledo and OhioLINK.