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ucin1025721991.pdf (38.57 MB)
ETD Abstract Container
Abstract Header
iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE
Author Info
KHAN, JAWAD BASIT
Permalink:
http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991
Abstract Details
Year and Degree
2002, MS, University of Cincinnati, Engineering : Computer Engineering.
Abstract
The iPACE-V1 (Image Processing Adaptive Computing Engine) is a portable, reconfigurable hardware platform, designed in the Digital Design Environments Laboratory at the University of Cincinnati. iPACE-V1 was specifically designed for real time, in-field image processing applications. Adaptive computing systems can be broadly defined as those systems which can modify their digital hardware to match the requirements of an application at hand. Field Programmable Gate Arrays (FPGA) are essential building blocks of such systems. iPACE-V1 has three Xilinx Virtex FPGAs: one houses the controller module, another acts as the main user programmable module and the data capture module is implemented in the last one. A maximum of 800,000 logic gates are available for computing in the form of FPGAs. Furthermore, 4 Mbytes of ZBT (Zero Bus turnaround) SRAM is interfaced. In addition to this, the board has a maximum of 1 Gigabytes SDRAM capacity. For non volatile data storage we have provided 4 Mbytes of FLASH ROM. Two serial ports along with a USB port are also provided. A camera is attached which provides video data and a small LCD is interfaced for image output. Every effort was made to incorporate as many debugging features, as possible: programmable clock, observable memories, partial reconfiguration and FPGA read-back are some features which top this list. Several controller cores have been written for various subsystems in iPACE-V1. These cores enable the user to efficiently exploit the available resources. This thesis discusses the hardware architecture of iPACE-V1 along with the VHDL controller cores. We also show the functional correctness and effectiveness of iPACE-V1. We have developed two demonstration examples for iPACE-V1: A frame grabber and a background elimination application. The frame grabber is implemented to demonstrate the functional correctness of the hardware. Whereas, the background elimination application is more performance oriented and is used to show the effectiveness of this architecture for realtime image processing.
Committee
Dr. Ranga Vemuri (Advisor)
Pages
139 p.
Subject Headings
Computer Science
Keywords
reconfigurable computing
;
adaptive computing
;
FPGAs
;
mobile computing
;
image processing
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Citations
KHAN, J. B. (2002).
iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE
[Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991
APA Style (7th edition)
KHAN, JAWAD.
iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE.
2002. University of Cincinnati, Master's thesis.
OhioLINK Electronic Theses and Dissertations Center
, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991.
MLA Style (8th edition)
KHAN, JAWAD. "iPACE-V1: A PORTAABLE ADAPTIVE COMPUTING ENGINE." Master's thesis, University of Cincinnati, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1025721991
Chicago Manual of Style (17th edition)
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Document number:
ucin1025721991
Download Count:
573
Copyright Info
© 2002, all rights reserved.
This open access ETD is published by University of Cincinnati and OhioLINK.