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ITERATIVE RELAXATION ALGORITHM: AN EFFICIENT AND IMPROVED METHOD FOR CIRCUIT SIMULATION USED IN SIERRA: VHDL-AMS SIMULATOR

BALAKRISHNAN, GEETA

Abstract Details

2002, MS, University of Cincinnati, Engineering : Computer Engineering.
Simulation is a means of validating and verifying the functionality of an electronic circuit. The success of any semiconductor industry depends greatly on the die-yield and throughput. Simulation is an excellent method to provide feedback to the designer when designing large systems, so that modifications in design and implementation can be done during the initial stages of design before the actual hardware implementation of the chip. Simulation helps the designer to identify the key factors affecting the design and try to enhance performance. VHDL-AMS is an extension of VHDL, the hardware description language supporting the digital circuit environment. The AMS extension enables modeling of analog and mixed signal circuits, thereby extending the modeling horizons. VHDL-AMS, an IEEE approved high-level design language for mixed signal multi-domain circuits support description of high-level systems with continuous dynamic behavior that can be specified as Ordinary Differential Algebraic Equations. The chief bottle-neck in mixed-signal simulation is speed. The solve time at each time step is large which in turn contributes to the total simulation time. Hence a method to improve the solve time is definitely a welcome, as it contributes to the overall performance improvement. The Relaxation algorithm studied and implemented in this thesis is a method explored to improve the performance of the simulator. It is based on the use of iterative algorithms as against the conventional direct method of solution. Spectral radius evaluation which further reduces the solve time from a complexity of O(n3) to O(n) is incorporated into the relax algorithm to further improve overall performance. This thesis proposes an improvement in speed of at least 5% for digital, analog and mixed circuits.
Dr. Harold W. Carter (Advisor)
82 p.

Recommended Citations

Citations

  • BALAKRISHNAN, G. (2002). ITERATIVE RELAXATION ALGORITHM: AN EFFICIENT AND IMPROVED METHOD FOR CIRCUIT SIMULATION USED IN SIERRA: VHDL-AMS SIMULATOR [Master's thesis, University of Cincinnati]. OhioLINK Electronic Theses and Dissertations Center. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1034358459

    APA Style (7th edition)

  • BALAKRISHNAN, GEETA. ITERATIVE RELAXATION ALGORITHM: AN EFFICIENT AND IMPROVED METHOD FOR CIRCUIT SIMULATION USED IN SIERRA: VHDL-AMS SIMULATOR. 2002. University of Cincinnati, Master's thesis. OhioLINK Electronic Theses and Dissertations Center, http://rave.ohiolink.edu/etdc/view?acc_num=ucin1034358459.

    MLA Style (8th edition)

  • BALAKRISHNAN, GEETA. "ITERATIVE RELAXATION ALGORITHM: AN EFFICIENT AND IMPROVED METHOD FOR CIRCUIT SIMULATION USED IN SIERRA: VHDL-AMS SIMULATOR." Master's thesis, University of Cincinnati, 2002. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1034358459

    Chicago Manual of Style (17th edition)